# 74LVC1G80GW

**Nexperia** · Flip Flops · SOT-353-5

74LVC1G80GW from Nexperia, in a SOT-353-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | input | Data input; data must meet the set-up and hold times around the LOW-to-HIGH CP transition, and input voltage is rated 0 V to 5.5 V under recommended operating conditions. |
| 2 | CP | input | Clock pulse input; the LOW-to-HIGH transition stores D into the flip-flop, and the Schmitt-trigger input is overvoltage tolerant to 5.5 V. |
| 3 | GND | power_in | Ground (0 V) reference for all voltages in the device. |
| 4 | Q | output | Data output that presents the complement of the stored D value; the output is disabled during power-down via IOFF circuitry and is rated for ±24 mA drive at VCC = 3.0 V. |
| 5 | VCC | power_in | Supply voltage; recommended operating range is 1.65 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-353-5 |
| Category | Logic |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 1.65 |  | 5.5 | V |  | 5 |
| input voltage | VI | 0 |  | 5.5 | V |  | 5 |
| output voltage, power-down mode | VO | 0 |  | 5.5 | V | Power-down mode; VCC = 0 V | 5 |
| ambient temperature | Tamb | -40 |  | 125 | °C |  | 5 |
| input transition rise and fall rate | Δt/ΔV |  |  | 20 | ns/V | VCC = 1.65 V to 2.7 V | 5 |
| input transition rise and fall rate | Δt/ΔV |  |  | 10 | ns/V | VCC = 2.7 V to 5.5 V | 5 |
| supply voltage | VCC | -0.5 |  | 6.5 | V |  | 5 |
| input clamping current | IIK | -50 |  |  | mA | VI < 0 V | 5 |
| input voltage | VI | -0.5 |  | 6.5 | V |  | 5 |
| output clamping current | IOK | -50 |  | 50 | mA | VO > VCC or VO < 0 V | 5 |
| output voltage, power-down mode | VO | -0.5 |  | 6.5 | V | Power-down mode; VCC = 0 V | 5 |
| output current | IO | -50 |  | 50 | mA | VO = 0 V to VCC | 5 |
| supply current | ICC |  |  | 100 | mA |  | 5 |
| ground current | IGND | -100 |  |  | mA |  | 5 |
| total power dissipation | Ptot |  |  | 250 | mW | Tamb = -40 °C to +125 °C | 5 |
| storage temperature | Tstg | -65 |  | 150 | °C |  | 5 |
| HIGH-level input voltage | VIH | 1.7 |  |  | V | VCC = 2.3 V to 2.7 V; Tamb = -40 °C to +125 °C | 7 |
| HIGH-level input voltage | VIH | 2 |  |  | V | VCC = 2.7 V to 3.6 V; Tamb = -40 °C to +125 °C | 7 |
| LOW-level input voltage | VIL |  |  | 0.7 | V | VCC = 2.3 V to 2.7 V; Tamb = -40 °C to +125 °C | 7 |
| LOW-level input voltage | VIL |  |  | 0.8 | V | VCC = 2.7 V to 3.6 V; Tamb = -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 0.95 |  |  | V | IO = -4 mA; VCC = 1.65 V; Tamb = -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 1.7 |  |  | V | IO = -8 mA; VCC = 2.3 V; Tamb = -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 1.9 |  |  | V | IO = -12 mA; VCC = 2.7 V; Tamb = -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 2 |  |  | V | IO = -24 mA; VCC = 3.0 V; Tamb = -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 3.4 |  |  | V | IO = -32 mA; VCC = 4.5 V; Tamb = -40 °C to +125 °C | 7 |
| LOW-level output voltage | VOL |  |  | 0.1 | V | IO = 100 μA; VCC = 1.65 V to 5.5 V; Tamb = -40 °C to +125 °C | 7 |
| LOW-level output voltage | VOL |  |  | 0.7 | V | IO = 4 mA; VCC = 1.65 V; Tamb = -40 °C to +125 °C | 7 |
| LOW-level output voltage | VOL |  |  | 0.45 | V | IO = 8 mA; VCC = 2.3 V; Tamb = -40 °C to +125 °C | 7 |
| LOW-level output voltage | VOL |  |  | 0.6 | V | IO = 12 mA; VCC = 2.7 V; Tamb = -40 °C to +125 °C | 7 |
| LOW-level output voltage | VOL |  |  | 0.8 | V | IO = 24 mA; VCC = 3.0 V; Tamb = -40 °C to +125 °C | 7 |
| input leakage current | II | -1 |  | 1 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V; Tamb = -40 °C to +125 °C | 7 |
| power-off leakage current | IOFF | -2 |  | 2 | μA | VCC = 0 V; VI or VO = 5.5 V; Tamb = -40 °C to +125 °C | 7 |
| supply current | ICC |  |  | 4 | μA | VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A; Tamb = -40 °C to +125 °C | 7 |
| additional supply current per pin | ΔICC |  |  | 500 | μA | VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A; Tamb = -40 °C to +125 °C | 7 |
| propagation delay CP to Q | tpd | 1 |  | 13 | ns | VCC = 1.65 V to 1.95 V; Tamb = -40 °C to +125 °C; see Fig. 8 | 8 |
| propagation delay CP to Q | tpd | 0.5 |  | 9 | ns | VCC = 2.3 V to 2.7 V; Tamb = -40 °C to +125 °C; see Fig. 8 | 8 |
| propagation delay CP to Q | tpd | 0.5 |  | 8 | ns | VCC = 2.7 V; Tamb = -40 °C to +125 °C; see Fig. 8 | 8 |
| propagation delay CP to Q | tpd | 0.9 |  | 6.5 | ns | VCC = 3.0 V to 3.6 V; Tamb = -40 °C to +125 °C; see Fig. 8 | 8 |
| propagation delay CP to Q | tpd | 0.5 |  | 6 | ns | VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C; see Fig. 8 | 8 |
| set-up time D to CP | tsu | 2.3 |  |  | ns | VCC = 1.65 V to 1.95 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| set-up time D to CP | tsu | 1.5 |  |  | ns | VCC = 2.3 V to 2.7 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| set-up time D to CP | tsu | 1.3 |  |  | ns | VCC = 3.0 V to 3.6 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| set-up time D to CP | tsu | 1.1 |  |  | ns | VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| hold time CP to D | th | 0 |  |  | ns | VCC = 1.65 V to 1.95 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| hold time CP to D | th | 0.5 |  |  | ns | VCC = 2.7 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| hold time CP to D | th | 0.9 |  |  | ns | VCC = 3.0 V to 3.6 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| pulse width CP | tW | 3 |  |  | ns | VCC = 1.65 V to 1.95 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| pulse width CP | tW | 2.5 |  |  | ns | VCC = 2.3 V to 2.7 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| pulse width CP | tW | 2 |  |  | ns | VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| maximum clock frequency | fmax | 160 |  |  | MHz | VCC = 1.65 V to 1.95 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |
| maximum clock frequency | fmax | 200 |  |  | MHz | VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C; see Fig. 9 | 8 |

## CAD (KiCad official)

- Symbol: `74LVC1G80GW`
- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`
- 3D model: SOT-353-5 (KiCad packages3D, STEP)
- 3D model files: `74lvc1g80gw-etched.step` / `74lvc1g80gw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc1g80gw.step` / `74lvc1g80gw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588911286977093632) (19 pp, sha256 `e72fff458dc6a5bd`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lvc1g80gw-datasheet.pdf)