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docs 74lvc1g58dw-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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74lvc1g58dw-7-etched.fit.json 74lvc1g58dw-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74lvc1g58dw-7-etched.glb 74lvc1g58dw-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74lvc1g58dw-7-etched.step 74lvc1g58dw-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74lvc1g58dw-7.glb Publish 0.1.0 · Ray 2mo ago
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page.json 74lvc1g58dw-7: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 28d ago
README.md 74lvc1g58dw-7: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74LVC1G58DW-7

Diodes Incorporated · Gates · SOT-363-6

74LVC1G58DW-7 from Diodes Incorporated, in a SOT-363-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 input Data input IN1 with Schmitt-trigger action. Accepts 0 V to 5.5 V regardless of VCC (5.5 V input tolerant). Unused inputs should be tied to VCC or GND.
2 GND power_in Ground reference (0 V). Return path for supply and I/O currents.
3 IN0 input Data input IN0 with Schmitt-trigger action. Accepts 0 V to 5.5 V regardless of VCC (5.5 V input tolerant). Unused inputs should be tied to VCC or GND.
4 Y output Data output with standard CMOS push-pull driver. Guaranteed drive of ±24 mA at VCC = 3 V; up to ±32 mA at VCC = 4.5 V. Logic function is determined by input tie pattern (AND/OR/NAND/NOR/XOR/buffer/inverter).
5 VCC power_in Supply voltage. Operating range 1.65 V to 5.5 V; 1.5 V minimum for data retention only. Absolute maximum -0.5 V to 6.5 V.
6 IN2 input Data input IN2 with Schmitt-trigger action. Accepts 0 V to 5.5 V regardless of VCC (5.5 V input tolerant). Unused inputs should be tied to VCC or GND.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-363-6
Category Logic
Pins 6

Ordering variants

  • 74LVC1G58DW-7
  • 74LVC1G58DW-7W6
  • 74LVC1G58DW-7FW4
  • 74LVC1G58DW-7FZ4

CAD (KiCad official)

  • Symbol: 74LVC1G58DW-7
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SOT-363-6 (KiCad packages3D, STEP)
  • 3D model files: 74lvc1g58dw-7-etched.step / 74lvc1g58dw-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc1g58dw-7.step / 74lvc1g58dw-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (15 pp, sha256 48273332f34aca04, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF