74LVC1G3208MDBVTEP

@@ -32,7 +32,7 @@         "number": "1",         "name": "A",         "type": "input",-        "description": "Logic input A of the OR-AND function Y = (A + B) \u00b7 C. CMOS input, 5.5 V tolerant regardless of VCC; VIH/VIL scale with VCC (e.g. VIH = 2.0 V, VIL = 0.8 V at VCC = 3.3 V). Input hysteresis \u2248 250 mV typ at 3.3 V."+        "description": "Logic input A of the OR-AND function Y = (A + B) · C. CMOS input, 5.5 V tolerant regardless of VCC; VIH/VIL scale with VCC (e.g. VIH = 2.0 V, VIL = 0.8 V at VCC = 3.3 V). Input hysteresis ≈ 250 mV typ at 3.3 V."       },       {         "number": "2",@@ -44,25 +44,25 @@         "number": "3",         "name": "B",         "type": "input",-        "description": "Logic input B of the OR-AND function Y = (A + B) \u00b7 C. CMOS input, 5.5 V tolerant; when tied to GND the device becomes a 2-input AND with Y = A \u00b7 C. Input hysteresis \u2248 250 mV typ at 3.3 V."+        "description": "Logic input B of the OR-AND function Y = (A + B) · C. CMOS input, 5.5 V tolerant; when tied to GND the device becomes a 2-input AND with Y = A · C. Input hysteresis ≈ 250 mV typ at 3.3 V."       },       {         "number": "4",         "name": "Y",         "type": "output",-        "description": "Push-pull CMOS logic output implementing Y = (A + B) \u00b7 C. Drive strength scales with VCC: \u00b14 mA at 1.65 V, \u00b116 mA at 3 V, \u00b124 mA at 3.3 V, \u00b132 mA at 4.5 V. High-impedance when Ioff / partial-power-down is engaged."+        "description": "Push-pull CMOS logic output implementing Y = (A + B) · C. Drive strength scales with VCC: ±4 mA at 1.65 V, ±16 mA at 3 V, ±24 mA at 3.3 V, ±32 mA at 4.5 V. High-impedance when Ioff / partial-power-down is engaged."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply rail. Operating range 1.65 V to 5.5 V (data retention only down to 1.5 V); absolute max 6.5 V. Bypass to GND with a 0.1 \u00b5F ceramic close to the pin. Typical ICC \u2264 12.5 \u00b5A (static)."+        "description": "Positive supply rail. Operating range 1.65 V to 5.5 V (data retention only down to 1.5 V); absolute max 6.5 V. Bypass to GND with a 0.1 µF ceramic close to the pin. Typical ICC ≤ 12.5 µA (static)."       },       {         "number": "6",         "name": "C",         "type": "input",-        "description": "Logic input C of the OR-AND function Y = (A + B) \u00b7 C. CMOS input, 5.5 V tolerant; when tied to VCC the device becomes a 2-input OR with Y = A + B. Input hysteresis \u2248 250 mV typ at 3.3 V."+        "description": "Logic input C of the OR-AND function Y = (A + B) · C. CMOS input, 5.5 V tolerant; when tied to VCC the device becomes a 2-input OR with Y = A + B. Input hysteresis ≈ 250 mV typ at 3.3 V."       }     ],     "provenance": {@@ -132,5 +132,8 @@     "docs/74lvc1g3208mdbvtep-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file