# 74LVC1G07GV

**TECH PUBLIC** · Logic Gates · SOT-23-5

74LVC1G07GV from TECH PUBLIC, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | A | input | Buffer input; accepts voltages up to 5.5V, with VIL max 0.35×VCC at 1.65-1.95V and 0.3×VCC at 4.5-5.5V. |
| 3 | GND | power_in | Ground pin (0V reference). |
| 4 | Y | output | Open-drain output that pulls low when A is low and is high-impedance (Z) when A is high, tolerating up to 5.5V. |
| 5 | VCC | power_in | Supply voltage pin, recommended operating range 1.65V to 5.5V (absolute maximum -0.5 to 6.5V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23-5 |
| Category | Logic |
| Pins | 5 |

## CAD (KiCad official)

- Symbol: `74LVC1G07GV`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `74lvc1g07gv-etched.step` / `74lvc1g07gv-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc1g07gv.step` / `74lvc1g07gv.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603009934171136000) (6 pp, sha256 `4ba18fd04fd22c16`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lvc1g07gv-datasheet.pdf)