74lvc1g02se-7: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo…
74lvc1g02se-7: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
74lvc1g02se-7: laser-etched CAD + chip hero (factory 2.0.0 backfill)
74lvc1g02se-7: stamp component.logic (74LVC1G02) from component-ocean
74lvc1g02se-7: publish the laser-etched STEP alongside the bare one
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <te…
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
74lvc1g02se-7: factory component page (tier=lcsc)
Initial commit: component/74lvc1g02se-7