component
74LVC1G02GW
Public Made by Adomby adom
Nexperia Gates, SOT-353-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdown74LVC1G02GW
Nexperia · Gates · SOT-353-5
74LVC1G02GW from Nexperia, in a SOT-353-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Data input B of the 2-input NOR gate. Schmitt-trigger CMOS input, overvoltage tolerant up to 5.5 V independent of VCC. Input leakage typ ±0.1 µA, max ±1 µA. |
| 2 | A | input | Data input A of the 2-input NOR gate. Schmitt-trigger CMOS input, overvoltage tolerant up to 5.5 V independent of VCC. Input leakage typ ±0.1 µA, max ±1 µA. |
| 3 | GND | power_in | Ground reference (0 V). All voltages in the datasheet are referenced to this pin. |
| 4 | Y | output | Data output Y = NOR(A, B). Push-pull CMOS output with ±24 mA drive at VCC = 3.0 V; latch-up performance exceeds 250 mA. |
| 5 | VCC | power_in | Positive supply voltage, 1.65 V to 5.5 V (absolute max 6.5 V). Quiescent supply current ICC typ 0.1 µA, max 4 µA. Decouple locally with a 100 nF ceramic capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-353-5 |
| Category | Logic |
| Pins | 5 |
Ordering variants
74LVC1G02GW74LVC1G02GWGV74LVC1G02GWGM74LVC1G02GWGN74LVC1G02GWGS74LVC1G02GWGX74LVC1G02GWGZ
CAD (KiCad official)
- Symbol:
74LVC1G02GW - Footprint:
Package_TO_SOT_SMD:SOT-353_SC-70-5 - 3D model: SOT-353-5 (KiCad packages3D, STEP)
- 3D model files:
74lvc1g02gw-etched.step/74lvc1g02gw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc1g02gw.step/74lvc1g02gw.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
74lvc1g02gw.step |
87 KB | You want the bare part, or you mark your own boards. |
74lvc1g02gw-etched.step |
1.8 MB | You want the part with 74LVC1G02GW already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 460 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (17 pp, sha256
4bd3838ab65f31f1, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).