# 74LVC1G02GV

**TECH PUBLIC** · Logic Gates · SOT-23-5

74LVC1G02GV from TECH PUBLIC, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Gate input A; NOR function Y = A+B inverted, with recommended input voltage 0 to 5.5V. |
| 2 | B | input | Gate input B; NOR function Y = A+B inverted, with recommended input voltage 0 to 5.5V. |
| 3 | GND | power_in | Ground pin (0V reference). |
| 4 | Y | output | Gate output Y, drives ±24mA at VCC=3.0V and swings 0 to VCC. |
| 5 | VCC | power_in | Supply voltage pin, recommended 2.0V to 5.5V (operation range 1.6V to 5.5V), absolute maximum -0.5 to +6.5V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOT-23-5 |
| Category | Logic |
| Pins | 5 |

## CAD (KiCad official)

- Symbol: `74LVC1G02GV`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `74lvc1g02gv-etched.step` / `74lvc1g02gv-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc1g02gv.step` / `74lvc1g02gv.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604430358221893632) (6 pp, sha256 `2113ca0516e4b41b`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lvc1g02gv-datasheet.pdf)