component
74LVC1G00M7
Public Made by Adomby adom
HGSEMI Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+116−8@@ -1,13 +1,126 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74lvc1g00m7",+ "title": "74LVC1G00M7",+ "brief": "HGSEMI Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "HGSEMI Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74lvc1g00m7" ],+ "component": {+ "mpn": "74LVC1G00M7",+ "manufacturer": "HGSEMI",+ "package": "SC-70-5",+ "pin_count": 5,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312081749_HGSEMI-74LVC1G00M7-TR_C19193439.pdf",+ "parts": {+ "symbol": "74lvc1g00m7.kicad_sym",+ "footprint": "74lvc1g00m7.kicad_mod",+ "model_3d": "74lvc1g00m7.glb",+ "model_3d_step": "74lvc1g00m7.step",+ "lbr": "74lvc1g00m7.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Logic input A of the 2-input NAND gate. CMOS input; VIH \u2265 0.7*VCC and VIL \u2264 0.3*VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (\u00b15 uA max)."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Logic input B of the 2-input NAND gate. CMOS input; VIH \u2265 0.7*VCC and VIL \u2264 0.3*VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (\u00b15 uA max)."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V) for the device."+ },+ {+ "number": "4",+ "name": "Y",+ "type": "output",+ "description": "NAND gate output: Y = NOT(A AND B). Push-pull CMOS output; sources up to 32 mA and sinks up to 32 mA at VCC = 4.5 V. Absolute max per-pin output current 25 mA (recommended)."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply input. Operating range 1.65 V to 5.5 V; absolute maximum 6.5 V. Bypass with a ceramic capacitor placed close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312081749_HGSEMI-74LVC1G00M7-TR_C19193439.pdf",+ "pages": 8,+ "sha256": "c6654ee8f8b8fc1b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 5,+ "described": 5,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "HGSEMI",+ "Package": "SC-70-5",+ "Category": "Logic",+ "Pins": "5"+ }+ },+ "variants": [+ {+ "mpn": "74LVC1G00M7",+ "kind": "packaging"+ },+ {+ "mpn": "74LVC1G00M7/TR",+ "kind": "packaging"+ },+ {+ "mpn": "74LVC1G00M7M5",+ "kind": "packaging"+ },+ {+ "mpn": "74LVC1G00M7M5/TR",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74lvc1g00m7"+ ],+ "discovery_pitch": "74LVC1G00M7 (HGSEMI) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +138,5 @@ "docs/74lvc1g00m7-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }