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Contents

README

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74LVC1G00GW

Nexperia · Gates · SOT-353

74LVC1G00GW from Nexperia, in a SOT-353. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B input Data input B to the 2-input NAND gate. Schmitt-trigger input; overvoltage tolerant to 5.5 V regardless of VCC. Input leakage typ ±0.1 µA, max ±1 µA.
2 A input Data input A to the 2-input NAND gate. Schmitt-trigger input; overvoltage tolerant to 5.5 V regardless of VCC. Input leakage typ ±0.1 µA, max ±1 µA.
3 GND power_in Ground reference (0 V). All voltages in the datasheet are referenced to this pin.
4 Y output Data output; Y = NAND(A, B). Push-pull CMOS output rated ±24 mA drive at VCC = 3.0 V. Output disabled when VCC = 0 V via IOFF circuitry.
5 VCC power_in Positive supply voltage, 1.65 V to 5.5 V (absolute max 6.5 V). Supply current ICC max 4 µA. Bypass with a 100 nF ceramic capacitor to GND close to the pin.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-353
Category Logic
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • 74LVC1G00GW
  • 74LVC1G00GWGV
  • 74LVC1G00GWGM
  • 74LVC1G00GWGN
  • 74LVC1G00GWGS
  • 74LVC1G00GWGX

CAD (KiCad official)

  • Symbol: 74LVC1G00GW
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SOT-353 (KiCad packages3D, STEP)
  • 3D model files: 74lvc1g00gw-etched.step / 74lvc1g00gw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc1g00gw.step / 74lvc1g00gw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 5263b49b15014824, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF