component

74LVC163PW

Public Made by Adom

by adom

Nexperia Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74lvc163pwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers 74lvc163pw: viewers · Ray 7d ago
74lvc163pw-etched.glb Publish 0.1.0 · Ray 7d ago
74lvc163pw-etched.step 74lvc163pw: factory component page (tier=mfr) · Ray 7d ago
74lvc163pw-hero.glb 74lvc163pw: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
74lvc163pw-hero.overlay.json Publish 0.1.0 · Ray 7d ago
74lvc163pw.glb Publish 0.1.0 · Ray 7d ago
74lvc163pw.kicad_mod Publish 0.1.0 · Ray 7d ago
74lvc163pw.kicad_sym Publish 0.1.0 · Ray 7d ago
74lvc163pw.lbr Publish 0.1.0 · Ray 7d ago
74lvc163pw.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

74LVC163PW

Nexperia · Counters, Dividers · TSSOP-16

74LVC163PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Synchronous master reset, active LOW; a LOW level sets Q0 to Q3 to LOW after the next positive clock transition, regardless of PE, CET and CEP.
2 CP input Clock input, edge-triggered on the LOW-to-HIGH transition, with all flip-flops clocked simultaneously on this edge.
3 D0 input Parallel data input D0, loaded into the counter on the positive clock edge when PE is LOW.
4 D1 input Parallel data input D1, loaded into the counter on the positive clock edge when PE is LOW.
5 D2 input Parallel data input D2, loaded into the counter on the positive clock edge when PE is LOW.
6 D3 input Parallel data input D3, loaded into the counter on the positive clock edge when PE is LOW.
7 CEP input Count enable input; both CEP and CET must be HIGH for the counter to count.
8 GND power_in Ground (0 V) reference for all voltages in the device.
9 PE input Parallel enable input, active LOW; a LOW level disables counting and loads D0 to D3 on the positive clock edge, subject to PE set-up and hold times.
10 CET input Count enable carry input; it is fed forward to enable the terminal count output TC and must be HIGH for counting.
11 Q3 output Flip-flop output Q3 (most significant bit), which can be preset HIGH or LOW.
12 Q2 output Flip-flop output Q2, which can be preset HIGH or LOW.
13 Q1 output Flip-flop output Q1, which can be preset HIGH or LOW.
14 Q0 output Flip-flop output Q0 (least significant bit), which can be preset HIGH or LOW.
15 TC output Terminal count output, HIGH when CET is HIGH and the counter is at terminal count (HHHH).
16 VCC power_in Supply voltage; recommended operating range is 1.65 V to 3.6 V, with functional operation down to 1.2 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 1.65 3.6 V 7
functional supply voltage VCC 1.2 V functional 7
input voltage VI 0 5.5 V 7
output voltage VO 0 V 7
ambient temperature Tamb -40 125 °C in free air 7
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 7
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 7
supply voltage VCC -0.5 6.5 V 6
input clamping current IIK -50 mA VI < 0 V 6
input voltage VI -0.5 6.5 V 6
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 6
output voltage VO -0.5 V 6
output current IO -50 50 mA VO = 0 V to VCC 6
supply current ICC 100 mA 6
ground current IGND -100 mA 6
storage temperature Tstg -65 150 °C 6
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 6
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V; -40 °C to +125 °C 7
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 7
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 0.12 V VCC = 1.2 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V; -40 °C to +125 °C 7
input leakage current II -20 0.1 20 μA VCC = 3.6 V; VI = 5.5 V or GND; -40 °C to +125 °C 7
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A; -40 °C to +125 °C 7
additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A; -40 °C to +125 °C 8
propagation delay CP to Qn tpd 1.5 7.4 16.7 ns CP to Qn; see Fig. 7; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 8
propagation delay CP to Qn tpd 2.6 4.2 9.4 ns CP to Qn; see Fig. 7; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 8
propagation delay CP to Qn tpd 1.5 4 9.5 ns CP to Qn; see Fig. 7; VCC = 2.7 V; -40 °C to +125 °C 8
propagation delay CP to Qn tpd 1.5 3.8 9.5 ns CP to Qn; see Fig. 7; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 8
propagation delay CP to TC tpd 1.9 8.5 18.1 ns CP to TC; see Fig. 7; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 8
propagation delay CP to TC tpd 3 4.8 10.2 ns CP to TC; see Fig. 7; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 8
propagation delay CP to TC tpd 1.5 4.6 10.5 ns CP to TC; see Fig. 7; VCC = 2.7 V; -40 °C to +125 °C 8
propagation delay CP to TC tpd 1.5 4.3 10 ns CP to TC; see Fig. 7; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 8
propagation delay CET to TC tpd 1.5 6.3 14.6 ns CET to TC; see Fig. 8; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 8
propagation delay CET to TC tpd 2.3 3.6 8.2 ns CET to TC; see Fig. 8; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 8
propagation delay CET to TC tpd 1.5 3.9 9 ns CET to TC; see Fig. 8; VCC = 2.7 V; -40 °C to +125 °C 8
propagation delay CET to TC tpd 1.5 3.3 8 ns CET to TC; see Fig. 8; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 8
pulse width tW 6 ns CP HIGH or LOW; see Fig. 7; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 8
pulse width tW 5 ns CP HIGH or LOW; see Fig. 7; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 8
pulse width tW 4 1.2 ns CP HIGH or LOW; see Fig. 7; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 8
maximum frequency fmax 80 ns VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 9
maximum frequency fmax 100 ns VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 9
maximum frequency fmax 120 MHz VCC = 2.7 V; -40 °C to +125 °C 9
maximum frequency fmax 120 200 MHz VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 9
set-up time tsu 8.5 ns CEP, CET to CP; see Fig. 11; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 9
set-up time tsu 6.5 ns CEP, CET to CP; see Fig. 11; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 9
set-up time tsu 5.5 ns CEP, CET to CP; see Fig. 11; VCC = 2.7 V; -40 °C to +125 °C 9
set-up time tsu 5 2.1 ns CEP, CET to CP; see Fig. 11; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 9

CAD (KiCad official)

  • Symbol: 74LVC163PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74lvc163pw-etched.step / 74lvc163pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc163pw.step / 74lvc163pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 a8caaaa11b736127, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF