# 74LVC157ABQ

**Nexperia** · Logic ICs · DHVQFN-16-EP(2.5x3.5)

74LVC157ABQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | input | Common data select input: HIGH selects data source 1 and LOW selects data source 0 for all four multiplexers. |
| 2 | 1I0 | input | Data input from source 0 for multiplexer 1, selected when S is LOW and E is LOW. |
| 3 | 1I1 | input | Data input from source 1 for multiplexer 1, selected when S is HIGH and E is LOW. |
| 4 | 1Y | output | Multiplexer 1 output, forced LOW when E is HIGH. |
| 5 | 2I0 | input | Data input from source 0 for multiplexer 2, selected when S is LOW and E is LOW. |
| 6 | 2I1 | input | Data input from source 1 for multiplexer 2, selected when S is HIGH and E is LOW. |
| 7 | 2Y | output | Multiplexer 2 output, forced LOW when E is HIGH. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | 3Y | output | Multiplexer 3 output, forced LOW when E is HIGH. |
| 10 | 3I1 | input | Data input from source 1 for multiplexer 3, selected when S is HIGH and E is LOW. |
| 11 | 3I0 | input | Data input from source 0 for multiplexer 3, selected when S is LOW and E is LOW. |
| 12 | 4Y | output | Multiplexer 4 output, forced LOW when E is HIGH. |
| 13 | 4I1 | input | Data input from source 1 for multiplexer 4, selected when S is HIGH and E is LOW. |
| 14 | 4I0 | input | Data input from source 0 for multiplexer 4, selected when S is LOW and E is LOW. |
| 15 | E | input | Enable input (active LOW for data selection); a HIGH forces all outputs 1Y to 4Y LOW. |
| 16 | VCC | power_in | Supply voltage; 1.2 V to 3.6 V wide range for operation, with 1.65 V minimum in recommended conditions. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-16-EP(2.5x3.5) |
| Category | Logic ICs |
| Pins | 17 |

## CAD (KiCad official)

- Symbol: `74LVC157ABQ`
- Footprint: `Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm`
- 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `74lvc157abq-etched.step` / `74lvc157abq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc157abq.step` / `74lvc157abq.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74LVC157ABQ.pdf) (15 pp, sha256 `4a4064e302063e53`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lvc157abq-datasheet.pdf)