component
74LVC14APW-Q100J
Public Made by Adomby adom
Nexperia Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LVC14APW-Q100J
Nexperia · Inverters · TSSOP-14
74LVC14APW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of Schmitt-trigger inverter 1; accepts up to 5.5 V (5 V tolerant), with unlimited input rise and fall times. |
| 2 | 1Y | output | Data output of inverter 1, the logic inverse of 1A; output voltage is limited to 0 V to VCC. |
| 3 | 2A | input | Data input of Schmitt-trigger inverter 2; accepts up to 5.5 V (5 V tolerant), with unlimited input rise and fall times. |
| 4 | 2Y | output | Data output of inverter 2, the logic inverse of 2A; output voltage is limited to 0 V to VCC. |
| 5 | 3A | input | Data input of Schmitt-trigger inverter 3; accepts up to 5.5 V (5 V tolerant), with unlimited input rise and fall times. |
| 6 | 3Y | output | Data output of inverter 3, the logic inverse of 3A; output voltage is limited to 0 V to VCC. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 4Y | output | Data output of inverter 4, the logic inverse of 4A; output voltage is limited to 0 V to VCC. |
| 9 | 4A | input | Data input of Schmitt-trigger inverter 4; accepts up to 5.5 V (5 V tolerant), with unlimited input rise and fall times. |
| 10 | 5Y | output | Data output of inverter 5, the logic inverse of 5A; output voltage is limited to 0 V to VCC. |
| 11 | 5A | input | Data input of Schmitt-trigger inverter 5; accepts up to 5.5 V (5 V tolerant), with unlimited input rise and fall times. |
| 12 | 6Y | output | Data output of inverter 6, the logic inverse of 6A; output voltage is limited to 0 V to VCC. |
| 13 | 6A | input | Data input of Schmitt-trigger inverter 6; accepts up to 5.5 V (5 V tolerant), with unlimited input rise and fall times. |
| 14 | VCC | power_in | Supply voltage, 1.65 V to 3.6 V recommended (functional down to 1.2 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 1.65 | 3.6 | V | 4 | ||
| supply voltage (functional) | VCC | 1.2 | V | functional | 4 | ||
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage | VO | 0 | V | 4 | |||
| ambient temperature | Tamb | -40 | 125 | °C | 4 | ||
| supply voltage | VCC | -0.5 | 6.5 | V | 3 | ||
| input voltage | VI | -0.5 | 6.5 | V | 3 | ||
| output voltage | VO | -0.5 | V | 3 | |||
| input clamping current | IIK | -50 | mA | VI < 0 V | 3 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 V | 3 | |
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 3 | |
| supply current | ICC | 100 | mA | 3 | |||
| ground current | IGND | -100 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| HIGH-level output voltage | VOH | 1.05 | V | IO = -4 mA; VCC = 1.65 V | 4 | ||
| HIGH-level output voltage | VOH | 1.65 | V | IO = -8 mA; VCC = 2.3 V | 4 | ||
| HIGH-level output voltage | VOH | 2.05 | V | IO = -12 mA; VCC = 2.7 V | 4 | ||
| HIGH-level output voltage | VOH | 2.25 | V | IO = -18 mA; VCC = 3.0 V | 4 | ||
| HIGH-level output voltage | VOH | 2 | V | IO = -24 mA; VCC = 3.0 V | 4 | ||
| LOW-level output voltage | VOL | 0.3 | V | IO = 100 μA; VCC = 1.65 V to 3.6 V | 4 | ||
| LOW-level output voltage | VOL | 0.65 | V | IO = 4 mA; VCC = 1.65 V | 4 | ||
| LOW-level output voltage | VOL | 0.8 | V | IO = 8 mA; VCC = 2.3 V | 4 | ||
| LOW-level output voltage | VOL | 0.6 | V | IO = 12 mA; VCC = 2.7 V | 4 | ||
| input leakage current | II | -20 | 0.1 | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND | 4 |
| supply current | ICC | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 4 | |
| additional supply current | ΔICC | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 4 | |
| propagation delay nA to nY | tpd | 1 | 6.1 | 14.7 | ns | VCC = 1.65 V to 1.95 V; see Fig. 6 | 5 |
| propagation delay nA to nY | tpd | 1.5 | 3.5 | 10 | ns | VCC = 2.3 V to 2.7 V; see Fig. 6 | 5 |
| propagation delay nA to nY | tpd | 1.5 | 3.6 | 9.5 | ns | VCC = 2.7 V; see Fig. 6 | 5 |
| propagation delay nA to nY | tpd | 1 | 3.2 | 8 | ns | VCC = 3.0 V to 3.6 V; see Fig. 6 | 5 |
| output skew time | tsk(o) | 1.5 | ns | VCC = 3.0 V to 3.6 V; per buffer; VI = GND to VCC | 5 | ||
| positive-going threshold voltage | VT+ | 0.2 | 1 | V | VCC = 1.2 V | 7 | |
| positive-going threshold voltage | VT+ | 0.4 | 1.3 | V | VCC = 1.65 V | 7 | |
| positive-going threshold voltage | VT+ | 0.6 | 1.5 | V | VCC = 1.95 V | 7 | |
| positive-going threshold voltage | VT+ | 0.8 | 1.7 | V | VCC = 2.3 V | 7 | |
| positive-going threshold voltage | VT+ | 0.9 | 1.7 | V | VCC = 2.5 V | 7 | |
| positive-going threshold voltage | VT+ | 1.1 | 2 | V | VCC = 2.7 V | 7 | |
| positive-going threshold voltage | VT+ | 1.2 | 2 | V | VCC = 3 V | 7 | |
| negative-going threshold voltage | VT- | 0.12 | 0.75 | V | VCC = 1.2 V | 7 | |
| negative-going threshold voltage | VT- | 0.15 | 0.85 | V | VCC = 1.65 V | 7 | |
| negative-going threshold voltage | VT- | 0.25 | 0.95 | V | VCC = 1.95 V | 7 | |
| negative-going threshold voltage | VT- | 0.4 | 1.1 | V | VCC = 2.3 V | 7 | |
| negative-going threshold voltage | VT- | 0.4 | 1.2 | V | VCC = 2.5 V | 7 | |
| negative-going threshold voltage | VT- | 0.8 | 1.4 | V | VCC = 2.7 V | 7 | |
| negative-going threshold voltage | VT- | 0.8 | 1.5 | V | VCC = 3 V | 7 | |
| hysteresis voltage (VT+ - VT-) | VH | 0.1 | 1 | V | VCC = 1.2 V | 7 | |
| hysteresis voltage (VT+ - VT-) | VH | 0.2 | 1.15 | V | VCC = 1.65 V | 7 | |
| hysteresis voltage (VT+ - VT-) | VH | 0.2 | 1.25 | V | VCC = 1.95 V | 7 | |
| hysteresis voltage (VT+ - VT-) | VH | 0.3 | 1.3 | V | VCC = 2.3 V | 7 | |
| hysteresis voltage (VT+ - VT-) | VH | 0.3 | 1.1 | V | VCC = 2.7 V | 7 | |
| hysteresis voltage (VT+ - VT-) | VH | 0.3 | 1.2 | V | VCC = 3 V | 7 |
CAD (KiCad official)
- Symbol:
74LVC14APW-Q100J - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74lvc14apw-q100j-etched.step/74lvc14apw-q100j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc14apw-q100j.step/74lvc14apw-q100j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (14 pp, sha256
7a7db37445afddcf, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).