component
74LVC139BQ
Public Made by Adomby adom
Nexperia Signal Switches, Multiplexers, Decoders, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 6d ago |
| viewers | 6d ago |
| 74lvc139bq-etched.glb | 6d ago |
| 74lvc139bq-etched.step | 6d ago |
| 74lvc139bq-hero.glb | 6d ago |
| 74lvc139bq-hero.overlay.json | 6d ago |
| 74lvc139bq.glb | 6d ago |
| 74lvc139bq.kicad_mod | 6d ago |
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| 74lvc139bq.lbr | 6d ago |
| 74lvc139bq.step | 6d ago |
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| README.md | 6d ago |
74LVC139BQ
Nexperia · Signal Switches, Multiplexers, Decoders · DHVQFN-16-EP(2.5x3.5)
74LVC139BQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1E | input | Enable input for decoder 1, active LOW; when nE is HIGH all outputs are forced HIGH. |
| 2 | 1A0 | input | Address input A0 for decoder 1, Schmitt-trigger input that accepts up to 5.5 V and is tolerant of slow edges. |
| 3 | 1A1 | input | Address input A1 for decoder 1, Schmitt-trigger input that accepts up to 5.5 V and is tolerant of slow edges. |
| 4 | 1Y0 | output | Mutually exclusive output 0 of decoder 1, driven LOW when selected with nE LOW. |
| 5 | 1Y1 | output | Mutually exclusive output 1 of decoder 1, driven LOW when selected with nE LOW. |
| 6 | 1Y2 | output | Mutually exclusive output 2 of decoder 1, driven LOW when selected with nE LOW. |
| 7 | 1Y3 | output | Mutually exclusive output 3 of decoder 1, driven LOW when selected with nE LOW. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | 2Y3 | output | Mutually exclusive output 3 of decoder 2, driven LOW when selected with nE LOW. |
| 10 | 2Y2 | output | Mutually exclusive output 2 of decoder 2, driven LOW when selected with nE LOW. |
| 11 | 2Y1 | output | Mutually exclusive output 1 of decoder 2, driven LOW when selected with nE LOW. |
| 12 | 2Y0 | output | Mutually exclusive output 0 of decoder 2, driven LOW when selected with nE LOW. |
| 13 | 2A1 | input | Address input A1 for decoder 2, Schmitt-trigger input that accepts up to 5.5 V and is tolerant of slow edges. |
| 14 | 2A0 | input | Address input A0 for decoder 2, Schmitt-trigger input that accepts up to 5.5 V and is tolerant of slow edges. |
| 15 | 2E | input | Enable input for decoder 2, active LOW; when nE is HIGH all outputs are forced HIGH. |
| 16 | VCC | power_in | Positive supply voltage, 1.65 V to 3.6 V recommended operating range. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-16-EP(2.5x3.5) |
| Category | Logic |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 6.5 | V | 3 | ||
| input clamping current | IIK | -50 | mA | VI < 0 | 3 | ||
| input voltage | VI | -0.5 | 6.5 | V | 3 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 V | 3 | |
| output voltage | VO | -0.5 | V | 3 | |||
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 3 | |
| supply current | ICC | 100 | mA | 3 | |||
| ground current | IGND | -100 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| supply voltage | VCC | 1.65 | 3.6 | V | 4 | ||
| functional supply voltage | 1.2 | V | functional | 4 | |||
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage | VO | 0 | V | max VCC | 4 | ||
| ambient temperature | Tamb | -40 | 125 | °C | in free air | 4 | |
| input transition rise and fall rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 1.65 V to 2.7 V | 4 | |
| input transition rise and fall rate | Δt/ΔV | 0 | 10 | ns/V | VCC = 2.7 V to 3.6 V | 4 | |
| HIGH-level input voltage | VIH | 1.08 | V | VCC = 1.2 V | 4 | ||
| HIGH-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| LOW-level input voltage | VIL | 0.12 | V | VCC = 1.2 V | 4 | ||
| LOW-level input voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| HIGH-level output voltage | VOH | 1.05 | 1.2 | V | IO = -4 mA; VCC = 1.65 V | 4 | |
| HIGH-level output voltage | VOH | 1.65 | 1.8 | V | IO = -8 mA; VCC = 2.3 V | 4 | |
| HIGH-level output voltage | VOH | 2.05 | 2.2 | V | IO = -12 mA; VCC = 2.7 V | 4 | |
| HIGH-level output voltage | VOH | 2.25 | 2.4 | V | IO = -18 mA; VCC = 3.0 V | 4 | |
| HIGH-level output voltage | VOH | 2 | 2.2 | V | IO = -24 mA; VCC = 3.0 V | 4 | |
| LOW-level output voltage | VOL | 0.3 | V | IO = 100 μA; VCC = 1.65 V to 3.6 V | 4 | ||
| LOW-level output voltage | VOL | 0.65 | V | IO = 4 mA; VCC = 1.65 V | 4 | ||
| LOW-level output voltage | VOL | 0.8 | V | IO = 8 mA; VCC = 2.3 V | 4 | ||
| LOW-level output voltage | VOL | 0.6 | V | IO = 12 mA; VCC = 2.7 V | 4 | ||
| input leakage current | II | -20 | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND | 4 | |
| supply current | ICC | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 4 | |
| additional supply current | ΔICC | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 5 | |
| propagation delay nAn to nYn | tpd | 0.5 | 4.7 | 11.3 | ns | nAn to Yn; see Fig. 4; VCC = 1.65 V to 1.95 V | 5 |
| propagation delay nAn to nYn | tpd | 1 | 2.8 | 6.5 | ns | nAn to Yn; see Fig. 4; VCC = 2.3 V to 2.7 V | 5 |
| propagation delay nAn to nYn | tpd | 1 | 3 | 8 | ns | nAn to Yn; see Fig. 4; VCC = 2.7 V | 5 |
| propagation delay nAn to nYn | tpd | 1 | 2.5 | 7 | ns | nAn to Yn; see Fig. 4; VCC = 3.0 V to 3.6 V | 5 |
| propagation delay nE to nYn | tpd | 1.5 | 4.5 | 10.7 | ns | nE to Yn; see Fig. 5; VCC = 1.65 V to 1.95 V | 5 |
| propagation delay nE to nYn | tpd | 2.1 | 2.7 | 6.1 | ns | nE to Yn; see Fig. 5; VCC = 2.3 V to 2.7 V | 5 |
| propagation delay nE to nYn | tpd | 1 | 2.8 | 7 | ns | nE to Yn; see Fig. 5; VCC = 2.7 V | 5 |
| propagation delay nE to nYn | tpd | 1 | 2.4 | 6.5 | ns | nE to Yn; see Fig. 5; VCC = 3.0 V to 3.6 V | 5 |
| output skew time | tsk(o) | 1.5 | ns | VCC = 3.0 V to 3.6 V | 5 | ||
| power dissipation derating (DHVQFN16, SOT763-1) | Ptot | 11.2 | mW/K | derates linearly above 106 °C | 3 |
CAD (KiCad official)
- Symbol:
74LVC139BQ - Footprint:
Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm - 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74lvc139bq-etched.step/74lvc139bq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc139bq.step/74lvc139bq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
0724ea5fe6c2fc18, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).