component
74LVC138AD
Public Made by Adomby adom
Nexperia Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LVC138AD
Nexperia · Signal Switches, Multiplexers, Decoders · SOIC-16
74LVC138AD from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input A0 of the 3-to-8 decoder; inputs are Schmitt-trigger buffered and overvoltage tolerant to 5.5 V. |
| 2 | A1 | input | Address input A1 of the 3-to-8 decoder; inputs are Schmitt-trigger buffered and overvoltage tolerant to 5.5 V. |
| 3 | A2 | input | Address input A2 of the 3-to-8 decoder; inputs are Schmitt-trigger buffered and overvoltage tolerant to 5.5 V. |
| 4 | E1 | input | Active-LOW enable input; all outputs stay HIGH unless E1 and E2 are LOW and E3 is HIGH. |
| 5 | E2 | input | Active-LOW enable input; all outputs stay HIGH unless E1 and E2 are LOW and E3 is HIGH. |
| 6 | E3 | input | Active-HIGH enable input; all outputs stay HIGH unless E1 and E2 are LOW and E3 is HIGH. |
| 7 | Y7 | output | Mutually exclusive decoder output for address 7; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages; not an electrical or mechanical requirement to solder pad (SOT763 note) and applies to SO16 ground pin. |
| 9 | Y6 | output | Mutually exclusive decoder output for address 6; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 10 | Y5 | output | Mutually exclusive decoder output for address 5; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 11 | Y4 | output | Mutually exclusive decoder output for address 4; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 12 | Y3 | output | Mutually exclusive decoder output for address 3; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 13 | Y2 | output | Mutually exclusive decoder output for address 2; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 14 | Y1 | output | Mutually exclusive decoder output for address 1; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 15 | Y0 | output | Mutually exclusive decoder output for address 0; goes LOW when selected and HIGH otherwise, with output current limited to ±50 mA. |
| 16 | VCC | power_in | Supply voltage; recommended 1.65 V to 3.6 V, functional down to 1.2 V, with absolute maximum of 6.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage (absolute maximum) | VCC | -0.5 | 6.5 | V | 4 | ||
| input clamping current | IIK | -50 | mA | VI < 0 V | 4 | ||
| input voltage (absolute maximum) | VI | -0.5 | 6.5 | V | 4 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 V | 4 | |
| output voltage (absolute maximum) | VO | -0.5 | V | output HIGH or LOW state | 4 | ||
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 4 | |
| supply current (absolute maximum) | ICC | 100 | mA | 4 | |||
| ground current | IGND | -100 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| supply voltage | VCC | 1.65 | 3.6 | V | 4 | ||
| functional supply voltage | VCC | 1.2 | V | functional | 4 | ||
| input voltage (recommended) | VI | 0 | 5.5 | V | 4 | ||
| output voltage (recommended) | VO | 0 | V | output HIGH or LOW state | 4 | ||
| ambient temperature | Tamb | -40 | 125 | °C | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 1.65 V to 2.7 V | 4 | |
| input transition rise and fall rate | Δt/ΔV | 0 | 10 | ns/V | VCC = 2.7 V to 3.6 V | 4 | |
| HIGH-level input voltage | VIH | 1.08 | V | VCC = 1.2 V | 5 | ||
| HIGH-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 5 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V | 5 | ||
| LOW-level input voltage | VIL | 0.12 | V | VCC = 1.2 V | 5 | ||
| LOW-level input voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 5 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V | 5 | ||
| HIGH-level output voltage | VOH | 1.05 | V | VI = VIH or VIL; IO = -4 mA; VCC = 1.65 V | 5 | ||
| HIGH-level output voltage | VOH | 1.65 | V | VI = VIH or VIL; IO = -8 mA; VCC = 2.3 V | 5 | ||
| HIGH-level output voltage | VOH | 2.05 | V | VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V | 5 | ||
| HIGH-level output voltage | VOH | 2.25 | V | VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V | 5 | ||
| HIGH-level output voltage | VOH | 2 | V | VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V | 5 | ||
| LOW-level output voltage | VOL | 0.3 | V | VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V | 5 | ||
| LOW-level output voltage | VOL | 0.65 | V | VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V | 5 | ||
| LOW-level output voltage | VOL | 0.8 | V | VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V | 5 | ||
| LOW-level output voltage | VOL | 0.6 | V | VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V | 5 | ||
| input leakage current | II | -20 | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND | 5 | |
| supply current | ICC | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 5 | |
| additional supply current | ΔICC | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 5 | |
| propagation delay An to Yn | tpd | 1.5 | 5.2 | 12.7 | ns | VCC = 1.65 V to 1.95 V; see Fig. 7 | 6 |
| propagation delay An to Yn | tpd | 1.5 | 3 | 7.3 | ns | VCC = 2.3 V to 2.7 V; see Fig. 7 | 6 |
| propagation delay An to Yn | tpd | 1.5 | 3.2 | 8.5 | ns | VCC = 2.7 V; see Fig. 7 | 6 |
| propagation delay An to Yn | tpd | 1 | 2.7 | 7.5 | ns | VCC = 3.0 V to 3.6 V; see Fig. 7 | 6 |
| propagation delay E3 to Yn | tpd | 1 | 5.5 | 12.5 | ns | VCC = 1.65 V to 1.95 V; see Fig. 7 | 6 |
| propagation delay E3 to Yn | tpd | 1.5 | 3.2 | 7.1 | ns | VCC = 2.3 V to 2.7 V; see Fig. 7 | 6 |
| propagation delay E3 to Yn | tpd | 1.5 | 3.3 | 8.5 | ns | VCC = 2.7 V; see Fig. 7 | 6 |
| propagation delay E3 to Yn | tpd | 1 | 2.9 | 7.5 | ns | VCC = 3.0 V to 3.6 V; see Fig. 7 | 6 |
| propagation delay En to Yn | tpd | 1 | 5.6 | 12.8 | ns | VCC = 1.65 V to 1.95 V; see Fig. 8 | 6 |
| propagation delay En to Yn | tpd | 1.8 | 3.3 | 7.3 | ns | VCC = 2.3 V to 2.7 V; see Fig. 8 | 6 |
| propagation delay En to Yn | tpd | 1.5 | 3.4 | 8 | ns | VCC = 2.7 V; see Fig. 8 | 6 |
| propagation delay En to Yn | tpd | 1 | 2.9 | 7.5 | ns | VCC = 3.0 V to 3.6 V; see Fig. 8 | 6 |
| output skew time | tsk(o) | 1.5 | ns | 6 |
CAD (KiCad official)
- Symbol:
74LVC138AD - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
74lvc138ad-etched.step/74lvc138ad-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc138ad.step/74lvc138ad.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (14 pp, sha256
5be08e238780f500, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).