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74LVC11PW-Q100J

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Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC11PW-Q100J

Nexperia · Logic Gates · TSSOP-14

74LVC11PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of gate 1; the inputs accept voltages up to 5.5 V.
2 1B input Data input B of gate 1; the inputs accept voltages up to 5.5 V.
3 2A input Data input A of gate 2; the inputs accept voltages up to 5.5 V.
4 2B input Data input B of gate 2; the inputs accept voltages up to 5.5 V.
5 2C input Data input C of gate 2; the inputs accept voltages up to 5.5 V.
6 2Y output Data output of gate 2; the output voltage is limited to the range 0 V to VCC.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 3Y output Data output of gate 3; the output voltage is limited to the range 0 V to VCC.
9 3A input Data input A of gate 3; the inputs accept voltages up to 5.5 V.
10 3B input Data input B of gate 3; the inputs accept voltages up to 5.5 V.
11 3C input Data input C of gate 3; the inputs accept voltages up to 5.5 V.
12 1Y output Data output of gate 1; the output voltage is limited to the range 0 V to VCC.
13 1C input Data input C of gate 1; the inputs accept voltages up to 5.5 V.
14 VCC power_in Supply voltage; the recommended range is 1.65 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.65 3.6 V 4
Functional supply voltage 1.2 V functional 4
Input voltage VI 0 5.5 V 4
Output voltage VO 0 V 4
Ambient temperature Tamb -40 125 °C 4
Input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 4
Input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 4
Supply voltage VCC -0.5 6.5 V 3
Input clamping current IIK -50 mA VI < 0 V 3
Input voltage VI -0.5 6.5 V 3
Output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 3
Output voltage VO -0.5 V 3
Output current IO -50 50 mA VO = 0 V to VCC 3
Supply current ICC 100 mA 3
Ground current IGND -100 mA 3
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
Storage temperature Tstg -65 150 °C 3
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 4
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 4
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 4
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 4
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 4
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 4
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 4
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 4
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 4
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 4
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 4
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 4
Input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND 4
Supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 4
Additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 4
Input capacitance CI 5 pF VCC = 0 V to 3.6 V; VI = GND to VCC 5
Propagation delay tpd 14 ns VCC = 1.2 V 5
Propagation delay tpd 1 4.7 14.1 ns VCC = 1.65 V to 1.95 V; nA, nB, nC to nY; see Fig. 7 5
Propagation delay tpd 1.5 2.8 8 ns VCC = 2.3 V to 2.7 V; nA, nB, nC to nY; see Fig. 7 5
Propagation delay tpd 1.5 2.9 8.1 ns VCC = 2.7 V; nA, nB, nC to nY; see Fig. 7 5
Propagation delay tpd 1.5 2.5 7.2 ns VCC = 3.0 V to 3.6 V; nA, nB, nC to nY; see Fig. 7 5
Power dissipation capacitance CPD 3.1 pF VCC = 1.65 V to 1.95 V 5
Power dissipation capacitance CPD 6.2 pF VCC = 2.3 V to 2.7 V 5
Power dissipation capacitance CPD 9 pF VCC = 3.0 V to 3.6 V 5

CAD (KiCad official)

  • Symbol: 74LVC11PW-Q100J
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvc11pw-q100j-etched.step / 74lvc11pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc11pw-q100j.step / 74lvc11pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 8429e127055685c6, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF