component
74LVC10APW
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74LVC10APW
Nexperia · Logic Gates · TSSOP-14
74LVC10APW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 2 | 1B | input | Data input of gate 1 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 3 | 2A | input | Data input of gate 2 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 4 | 2B | input | Data input of gate 2 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 5 | 2C | input | Data input of gate 2 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 6 | 2Y | output | NAND output of gate 2; output voltage is limited to VCC + 0.5 V and output current to ±50 mA per Table 4. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | NAND output of gate 3; output voltage is limited to VCC + 0.5 V and output current to ±50 mA per Table 4. |
| 9 | 3A | input | Data input of gate 3 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 10 | 3B | input | Data input of gate 3 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 11 | 3C | input | Data input of gate 3 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 12 | 1Y | output | NAND output of gate 1; output voltage is limited to VCC + 0.5 V and output current to ±50 mA per Table 4. |
| 13 | 1C | input | Data input of gate 1 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 14 | VCC | power_in | Supply voltage; recommended range is 1.65 V to 3.6 V, with functional operation down to 1.2 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 1.65 | 3.6 | V | 3 | ||
| supply voltage functional | VCC | 1.2 | V | functional | 3 | ||
| input voltage | VI | 0 | 5.5 | V | 3 | ||
| ambient temperature in free air | Tamb | -40 | 125 | °C | 3 | ||
| input transition rise and fall rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 1.65 V to 2.7 V | 3 | |
| input transition rise and fall rate | Δt/ΔV | 0 | 10 | ns/V | VCC = 2.7 V to 3.6 V | 3 | |
| supply voltage | VCC | -0.5 | 6.5 | V | 3 | ||
| input clamping current | IIK | -50 | mA | VI < 0 V | 3 | ||
| input voltage | VI | -0.5 | 6.5 | V | 3 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 V | 3 | |
| output voltage | VO | -0.5 | V | 3 | |||
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 3 | |
| supply current | ICC | 100 | mA | 3 | |||
| ground current | IGND | -100 | mA | 3 | |||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| HIGH-level input voltage | VIH | 1.08 | V | VCC = 1.2 V | 4 | ||
| HIGH-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| LOW-level input voltage | VIL | 0.12 | V | VCC = 1.2 V | 4 | ||
| LOW-level input voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| HIGH-level output voltage | VOH | 1.05 | V | IO = -4 mA; VCC = 1.65 V | 4 | ||
| HIGH-level output voltage | VOH | 1.65 | V | IO = -8 mA; VCC = 2.3 V | 4 | ||
| HIGH-level output voltage | VOH | 2.05 | V | IO = -12 mA; VCC = 2.7 V | 4 | ||
| HIGH-level output voltage | VOH | 2.25 | V | IO = -18 mA; VCC = 3.0 V | 4 | ||
| HIGH-level output voltage | VOH | 2 | V | IO = -24 mA; VCC = 3.0 V | 4 | ||
| LOW-level output voltage | VOL | 0.3 | V | IO = 100 μA; VCC = 1.65 V to 3.6 V | 4 | ||
| LOW-level output voltage | VOL | 0.65 | V | IO = 4 mA; VCC = 1.65 V | 4 | ||
| LOW-level output voltage | VOL | 0.8 | V | IO = 8 mA; VCC = 2.3 V | 4 | ||
| LOW-level output voltage | VOL | 0.6 | V | IO = 12 mA; VCC = 2.7 V | 4 | ||
| input leakage current | II | -20 | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND | 4 | |
| supply current | ICC | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 4 | |
| additional supply current | ΔICC | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 4 | |
| propagation delay | tpd | 0.5 | 4.5 | 12.9 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 1.65 V to 1.95 V | 5 |
| propagation delay | tpd | 1 | 2.7 | 7.4 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 2.3 V to 2.7 V | 5 |
| propagation delay | tpd | 1.5 | 2.8 | 7.8 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 2.7 V | 5 |
| propagation delay | tpd | 1.5 | 2.4 | 6.6 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 3.0 V to 3.6 V | 5 |
| input capacitance | CI | 4 | pF | VCC = 0 V to 3.6 V; VI = GND to VCC | 4 | ||
| propagation delay | tpd | 13 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 1.2 V | 5 | ||
| power dissipation capacitance | CPD | 2.9 | pF | VCC = 1.65 V to 1.95 V | 5 | ||
| power dissipation capacitance | CPD | 6 | pF | VCC = 2.3 V to 2.7 V | 5 | ||
| power dissipation capacitance | CPD | 8.8 | pF | VCC = 3.0 V to 3.6 V | 5 | ||
| total power dissipation derating (SOT402-1 TSSOP14) | Ptot | 7.3 | mW/K | derates linearly above 81 °C | 3 |
CAD (KiCad official)
- Symbol:
74LVC10APW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74lvc10apw-etched.step/74lvc10apw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc10apw.step/74lvc10apw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
edc74cc7bf439d86, retrieved 2026-10-20, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74LVC10APW
**Nexperia** · Logic Gates · TSSOP-14
74LVC10APW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 2 | 1B | input | Data input of gate 1 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 3 | 2A | input | Data input of gate 2 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 4 | 2B | input | Data input of gate 2 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 5 | 2C | input | Data input of gate 2 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 6 | 2Y | output | NAND output of gate 2; output voltage is limited to VCC + 0.5 V and output current to ±50 mA per Table 4. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | NAND output of gate 3; output voltage is limited to VCC + 0.5 V and output current to ±50 mA per Table 4. |
| 9 | 3A | input | Data input of gate 3 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 10 | 3B | input | Data input of gate 3 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 11 | 3C | input | Data input of gate 3 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 12 | 1Y | output | NAND output of gate 1; output voltage is limited to VCC + 0.5 V and output current to ±50 mA per Table 4. |
| 13 | 1C | input | Data input of gate 1 (NAND, 3-input); datasheet states inputs accept up to 5.5 V and can be driven from 3.3 V or 5 V devices. |
| 14 | VCC | power_in | Supply voltage; recommended range is 1.65 V to 3.6 V, with functional operation down to 1.2 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 1.65 | | 3.6 | V | | 3 |
| supply voltage functional | VCC | 1.2 | | | V | functional | 3 |
| input voltage | VI | 0 | | 5.5 | V | | 3 |
| ambient temperature in free air | Tamb | -40 | | 125 | °C | | 3 |
| input transition rise and fall rate | Δt/ΔV | 0 | | 20 | ns/V | VCC = 1.65 V to 2.7 V | 3 |
| input transition rise and fall rate | Δt/ΔV | 0 | | 10 | ns/V | VCC = 2.7 V to 3.6 V | 3 |
| supply voltage | VCC | -0.5 | | 6.5 | V | | 3 |
| input clamping current | IIK | -50 | | | mA | VI < 0 V | 3 |
| input voltage | VI | -0.5 | | 6.5 | V | | 3 |
| output clamping current | IOK | -50 | | 50 | mA | VO > VCC or VO < 0 V | 3 |
| output voltage | VO | -0.5 | | | V | | 3 |
| output current | IO | -50 | | 50 | mA | VO = 0 V to VCC | 3 |
| supply current | ICC | | | 100 | mA | | 3 |
| ground current | IGND | -100 | | | mA | | 3 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| HIGH-level input voltage | VIH | 1.08 | | | V | VCC = 1.2 V | 4 |
| HIGH-level input voltage | VIH | 1.7 | | | V | VCC = 2.3 V to 2.7 V | 4 |
| HIGH-level input voltage | VIH | 2 | | | V | VCC = 2.7 V to 3.6 V | 4 |
| LOW-level input voltage | VIL | | | 0.12 | V | VCC = 1.2 V | 4 |
| LOW-level input voltage | VIL | | | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 |
| LOW-level input voltage | VIL | | | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 |
| HIGH-level output voltage | VOH | 1.05 | | | V | IO = -4 mA; VCC = 1.65 V | 4 |
| HIGH-level output voltage | VOH | 1.65 | | | V | IO = -8 mA; VCC = 2.3 V | 4 |
| HIGH-level output voltage | VOH | 2.05 | | | V | IO = -12 mA; VCC = 2.7 V | 4 |
| HIGH-level output voltage | VOH | 2.25 | | | V | IO = -18 mA; VCC = 3.0 V | 4 |
| HIGH-level output voltage | VOH | 2 | | | V | IO = -24 mA; VCC = 3.0 V | 4 |
| LOW-level output voltage | VOL | | | 0.3 | V | IO = 100 μA; VCC = 1.65 V to 3.6 V | 4 |
| LOW-level output voltage | VOL | | | 0.65 | V | IO = 4 mA; VCC = 1.65 V | 4 |
| LOW-level output voltage | VOL | | | 0.8 | V | IO = 8 mA; VCC = 2.3 V | 4 |
| LOW-level output voltage | VOL | | | 0.6 | V | IO = 12 mA; VCC = 2.7 V | 4 |
| input leakage current | II | -20 | | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND | 4 |
| supply current | ICC | | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 4 |
| additional supply current | ΔICC | | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 4 |
| propagation delay | tpd | 0.5 | 4.5 | 12.9 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 1.65 V to 1.95 V | 5 |
| propagation delay | tpd | 1 | 2.7 | 7.4 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 2.3 V to 2.7 V | 5 |
| propagation delay | tpd | 1.5 | 2.8 | 7.8 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 2.7 V | 5 |
| propagation delay | tpd | 1.5 | 2.4 | 6.6 | ns | nA, nB, nC to nY; see Fig. 4; VCC = 3.0 V to 3.6 V | 5 |
| input capacitance | CI | | 4 | | pF | VCC = 0 V to 3.6 V; VI = GND to VCC | 4 |
| propagation delay | tpd | | 13 | | ns | nA, nB, nC to nY; see Fig. 4; VCC = 1.2 V | 5 |
| power dissipation capacitance | CPD | | 2.9 | | pF | VCC = 1.65 V to 1.95 V | 5 |
| power dissipation capacitance | CPD | | 6 | | pF | VCC = 2.3 V to 2.7 V | 5 |
| power dissipation capacitance | CPD | | 8.8 | | pF | VCC = 3.0 V to 3.6 V | 5 |
| total power dissipation derating (SOT402-1 TSSOP14) | Ptot | | 7.3 | | mW/K | derates linearly above 81 °C | 3 |
## CAD (KiCad official)
- Symbol: `74LVC10APW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74lvc10apw-etched.step` / `74lvc10apw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc10apw.step` / `74lvc10apw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74LVC10APW.pdf) (12 pp, sha256 `edc74cc7bf439d86`, retrieved 2026-10-20, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74lvc10apw-datasheet.pdf)