component

74LVC08APW

Public Made by Adom

by adom

Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74lvc08apwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers 74lvc08apw: viewers · Ray 5d ago
74lvc08apw-etched.glb Publish 0.1.0 · Ray 5d ago
74lvc08apw-etched.step 74lvc08apw: factory component page (tier=mfr) · Ray 5d ago
74lvc08apw-hero.glb 74lvc08apw: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
74lvc08apw-hero.overlay.json Publish 0.1.0 · Ray 5d ago
74lvc08apw.glb Publish 0.1.0 · Ray 5d ago
74lvc08apw.kicad_mod Publish 0.1.0 · Ray 5d ago
74lvc08apw.kicad_sym Publish 0.1.0 · Ray 5d ago
74lvc08apw.lbr Publish 0.1.0 · Ray 5d ago
74lvc08apw.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

74LVC08APW

Nexperia · Logic Gates · TSSOP-14

74LVC08APW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of the first AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
2 1B input Data input 1B of the first AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
3 1Y output Data output 1Y of the first AND gate.
4 2A input Data input 2A of the second AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
5 2B input Data input 2B of the second AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
6 2Y output Data output 2Y of the second AND gate.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 3Y output Data output 3Y of the third AND gate.
9 3A input Data input 3A of the third AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
10 3B input Data input 3B of the third AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
11 4Y output Data output 4Y of the fourth AND gate.
12 4A input Data input 4A of the fourth AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
13 4B input Data input 4B of the fourth AND gate; inputs are Schmitt-trigger and overvoltage tolerant to 5.5 V.
14 VCC power_in Supply voltage; recommended operating range is 1.65 V to 3.6 V (functional down to 1.2 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 3
input clamping current IIK -50 mA VI < 0 V 3
input voltage VI -0.5 6.5 V 3
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 3
output current IO -50 50 mA VO = 0 V to VCC 3
supply current ICC 100 mA 3
ground current IGND -100 mA 3
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
storage temperature Tstg -65 150 °C 3
supply voltage VCC 1.65 3.6 V 3
functional supply voltage VCC 1.2 V functional 3
input voltage VI 0 5.5 V 3
ambient temperature Tamb -40 125 °C 3
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 3
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 3
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 4
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 4
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 4
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 4
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 4
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 4
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 4
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 4
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 4
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 4
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 4
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 4
input leakage current II -20 0.1 20 μA VCC = 3.6 V; VI = 5.5 V or GND 4
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 4
additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 4
propagation delay tpd 0.5 4.2 10.4 ns nA, nB to nY; see Fig. 4; VCC = 1.65 V to 1.95 V 5
propagation delay tpd 1 2.5 8 ns nA, nB to nY; see Fig. 4; VCC = 2.3 V to 2.7 V 5
propagation delay tpd 1.5 2.5 5.6 ns nA, nB to nY; see Fig. 4; VCC = 2.7 V 5
propagation delay tpd 1 2.3 4.8 ns nA, nB to nY; see Fig. 4; VCC = 3.0 V to 3.6 V 5
output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V 5
input capacitance CI 4 pF VCC = 0 V to 3.6 V; VI = GND to VCC 4
power dissipation capacitance CPD 4.4 pF VCC = 1.65 V to 1.95 V 5
power dissipation capacitance CPD 7.7 pF VCC = 2.3 V to 2.7 V 5
power dissipation capacitance CPD 10.5 pF VCC = 3.0 V to 3.6 V 5

CAD (KiCad official)

  • Symbol: 74LVC08APW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvc08apw-etched.step / 74lvc08apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc08apw.step / 74lvc08apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 d95a840ae04df82c, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF