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74LVC08AD

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Nexperia Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC08AD

Nexperia · Logic Gates · SOIC-14

74LVC08AD from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of the first AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
2 1B input Data input 1B of the first AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
3 1Y output Data output 1Y of the first AND gate, giving the AND of 1A and 1B.
4 2A input Data input 2A of the second AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
5 2B input Data input 2B of the second AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
6 2Y output Data output 2Y of the second AND gate, giving the AND of 2A and 2B.
7 GND power_in Ground (0 V) reference for all voltages.
8 3Y output Data output 3Y of the third AND gate, giving the AND of 3A and 3B.
9 3A input Data input 3A of the third AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
10 3B input Data input 3B of the third AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
11 4Y output Data output 4Y of the fourth AND gate, giving the AND of 4A and 4B.
12 4A input Data input 4A of the fourth AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
13 4B input Data input 4B of the fourth AND gate, overvoltage tolerant to 5.5 V and with Schmitt-trigger action.
14 VCC power_in Supply voltage, recommended 1.65 V to 3.6 V and functional down to 1.2 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.65 3.6 V 3
Functional supply voltage VCC 1.2 V functional 3
Input voltage VI 0 5.5 V 3
Output voltage VO 0 V output HIGH or LOW-state; max VCC 3
Ambient temperature Tamb -40 125 °C 3
Input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 3
Input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 3
Supply voltage VCC -0.5 6.5 V 3
Input clamping current IIK -50 mA VI < 0 V 3
Input voltage VI -0.5 6.5 V 3
Output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 3
Output voltage VO -0.5 V output HIGH or LOW-state; max VCC + 0.5 3
Output current IO -50 50 mA VO = 0 V to VCC 3
Supply current ICC 100 mA 3
Ground current IGND -100 mA 3
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
Storage temperature Tstg -65 150 °C 3
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 4
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 4
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 4
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 4
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 4
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 4
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 4
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 4
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 4
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 4
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 4
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 4
Input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND 4
Supply current ICC 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 4
Additional supply current ΔICC 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 4
Propagation delay tpd 0.5 10.4 ns VCC = 1.65 V to 1.95 V; nA, nB to nY; see Fig. 4 5
Propagation delay tpd 1 8 ns VCC = 2.3 V to 2.7 V; nA, nB to nY; see Fig. 4 5
Propagation delay tpd 1.5 5.6 ns VCC = 2.7 V; nA, nB to nY; see Fig. 4 5
Propagation delay tpd 1 4.8 ns VCC = 3.0 V to 3.6 V; nA, nB to nY; see Fig. 4 5
Output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V 5
Input capacitance CI 4 pF VCC = 0 V to 3.6 V; VI = GND to VCC 4
Propagation delay tpd 11 ns VCC = 1.2 V; nA, nB to nY; see Fig. 4 5
Power dissipation capacitance CPD 4.4 pF VCC = 1.65 V to 1.95 V 5
Power dissipation capacitance CPD 7.7 pF VCC = 2.3 V to 2.7 V 5
Power dissipation capacitance CPD 10.5 pF VCC = 3.0 V to 3.6 V 5

CAD (KiCad official)

  • Symbol: 74LVC08AD
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvc08ad-etched.step / 74lvc08ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc08ad.step / 74lvc08ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 d95a840ae04df82c, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed (audit)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF