# 74LVC07APW

**Nexperia** · Buffers, Drivers, Receivers, Transceivers · TSSOP-14

74LVC07APW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A with Schmitt-trigger action, tolerant of slower input rise and fall times and overvoltage tolerant to 5.5 V. |
| 2 | 1Y | output | Open-drain data output 1Y, with output voltage rated up to 5.5 V in active and high-impedance modes and output current up to 50 mA. |
| 3 | 2A | input | Data input 2A with Schmitt-trigger action, tolerant of slower input rise and fall times and overvoltage tolerant to 5.5 V. |
| 4 | 2Y | output | Open-drain data output 2Y, with output voltage rated up to 5.5 V in active and high-impedance modes and output current up to 50 mA. |
| 5 | 3A | input | Data input 3A with Schmitt-trigger action, tolerant of slower input rise and fall times and overvoltage tolerant to 5.5 V. |
| 6 | 3Y | output | Open-drain data output 3Y, with output voltage rated up to 5.5 V in active and high-impedance modes and output current up to 50 mA. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages in the datasheet. |
| 8 | 4Y | output | Open-drain data output 4Y, with output voltage rated up to 5.5 V in active and high-impedance modes and output current up to 50 mA. |
| 9 | 4A | input | Data input 4A with Schmitt-trigger action, tolerant of slower input rise and fall times and overvoltage tolerant to 5.5 V. |
| 10 | 5Y | output | Open-drain data output 5Y, with output voltage rated up to 5.5 V in active and high-impedance modes and output current up to 50 mA. |
| 11 | 5A | input | Data input 5A with Schmitt-trigger action, tolerant of slower input rise and fall times and overvoltage tolerant to 5.5 V. |
| 12 | 6Y | output | Open-drain data output 6Y, with output voltage rated up to 5.5 V in active and high-impedance modes and output current up to 50 mA. |
| 13 | 6A | input | Data input 6A with Schmitt-trigger action, tolerant of slower input rise and fall times and overvoltage tolerant to 5.5 V. |
| 14 | VCC | power_in | Supply voltage; recommended operating range 1.65 V to 5.5 V, functional down to 1.2 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| input voltage (functional, recommended supply) | VCC | 1.65 |  | 5.5 | V |  | 3 |
| functional supply voltage | VCC | 1.2 |  |  | V |  | 3 |
| input voltage | VI | 0 |  | 5.5 | V |  | 3 |
| output voltage, active mode | VO | 0 |  | 5.5 | V |  | 3 |
| output voltage, high-impedance mode | VO | 0 |  | 5.5 | V |  | 3 |
| ambient temperature | Tamb | -40 |  | 125 | °C |  | 3 |
| input transition rise and fall rate | Δt/ΔV | 0 |  | 20 | ns/V | VCC = 1.65 V to 2.7 V | 3 |
| input transition rise and fall rate | Δt/ΔV | 0 |  | 10 | ns/V | VCC = 2.7 V to 5.5 V | 3 |
| supply voltage | VCC | -0.5 |  | 6.5 | V |  | 3 |
| input clamping current | IIK | -50 |  |  | mA | VI < 0 V | 3 |
| input voltage | VI | -0.5 |  | 6.5 | V |  | 3 |
| output clamping current | IOK | -50 |  |  | mA | VO < 0 V | 3 |
| output voltage, active mode | VO | -0.5 |  | 6.5 | V |  | 3 |
| output voltage, high-impedance mode | VO | -0.5 |  | 6.5 | V |  | 3 |
| output current | IO |  |  | 50 | mA | VO = 0 V to VCC | 3 |
| supply current | ICC |  |  | 100 | mA |  | 3 |
| ground current | IGND | -100 |  |  | mA |  | 3 |
| total power dissipation | Ptot |  |  | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| HIGH-level input voltage | VIH | 1.08 |  |  | V | VCC = 1.2 V | 4 |
| HIGH-level input voltage | VIH | 0.65 |  |  | VCC | VCC = 1.65 V to 1.95 V | 4 |
| HIGH-level input voltage | VIH | 1.7 |  |  | V | VCC = 2.3 V to 2.7 V | 4 |
| HIGH-level input voltage | VIH | 2 |  |  | V | VCC = 2.7 V to 3.6 V | 4 |
| HIGH-level input voltage | VIH | 0.7 |  |  | VCC | VCC = 4.5 V to 5.5 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.12 | V | VCC = 1.2 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.35 | VCC | VCC = 1.65 V to 1.95 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.3 | VCC | VCC = 4.5 V to 5.5 V | 4 |
| LOW-level output voltage | VOL |  |  | 0.3 | V | VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 5.5 V | 4 |
| LOW-level output voltage | VOL |  |  | 0.6 | V | VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V | 4 |
| LOW-level output voltage | VOL |  |  | 0.75 | V | VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V | 4 |
| LOW-level output voltage | VOL |  |  | 0.8 | V | VI = VIH or VIL; IO = 24 mA; VCC = 3.0 V | 4 |
| input leakage current | II | -20 | 0.1 | 20 | μA | VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V | 4 |
| OFF-state output current | IOZ | -20 | 0.1 | 20 | μA | VI = VIH; VO = 5.5 V or GND; VCC = 1.65 V to 5.5 V | 4 |
| power-off leakage current | IOFF | -20 | 0.1 | 20 | μA | VI or VO = 5.5 V; VCC = 0 V | 4 |
| supply current | ICC |  | 0.1 | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 |
| additional supply current | ΔICC |  | 5 | 5000 | μA | per input pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 5.5 V | 4 |
| OFF-state to LOW propagation delay | tPZL | 0.5 | 1.7 | 6.5 | ns | nA to nY; see Fig. 6; VCC = 1.65 V to 1.95 V | 5 |
| OFF-state to LOW propagation delay | tPZL | 0.5 | 1.2 | 3.5 | ns | nA to nY; see Fig. 6; VCC = 2.3 V to 2.7 V | 5 |
| OFF-state to LOW propagation delay | tPZL | 0.5 | 1.8 | 4.5 | ns | nA to nY; see Fig. 6; VCC = 2.7 V | 5 |
| OFF-state to LOW propagation delay | tPZL | 0.5 | 1.2 | 4.5 | ns | nA to nY; see Fig. 6; VCC = 3.0 V to 3.6 V | 5 |
| OFF-state to LOW propagation delay | tPZL | 0.5 | 1.6 | 3.5 | ns | nA to nY; see Fig. 6; VCC = 4.5 V to 5.5 V | 5 |
| LOW to OFF-state propagation delay | tPLZ | 0.5 | 3 | 6.5 | ns | nA to nY; see Fig. 6; VCC = 1.65 V to 1.95 V | 5 |
| LOW to OFF-state propagation delay | tPLZ | 0.5 | 1.7 | 3.5 | ns | nA to nY; see Fig. 6; VCC = 2.3 V to 2.7 V | 5 |
| LOW to OFF-state propagation delay | tPLZ | 0.5 | 2.1 | 4.5 | ns | nA to nY; see Fig. 6; VCC = 2.7 V | 5 |
| LOW to OFF-state propagation delay | tPLZ | 0.5 | 2.5 | 4.5 | ns | nA to nY; see Fig. 6; VCC = 3.0 V to 3.6 V | 5 |
| LOW to OFF-state propagation delay | tPLZ | 0.5 | 1.6 | 3.5 | ns | nA to nY; see Fig. 6; VCC = 4.5 V to 5.5 V | 5 |

## CAD (KiCad official)

- Symbol: `74LVC07APW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74lvc07apw-etched.step` / `74lvc07apw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc07apw.step` / `74lvc07apw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881453740396544) (12 pp, sha256 `7e54baea5ee5b2c4`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lvc07apw-datasheet.pdf)