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74LVC04ABQ
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Nexperia Inverters, DHVQFN-14-EP(2.5x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74LVC04ABQ
Nexperia · Inverters · DHVQFN-14-EP(2.5x3)
74LVC04ABQ from Nexperia, in a DHVQFN-14-EP(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverter gate 1 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 2 | 1Y | output | Data output of inverter gate 1 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 3 | 2A | input | Data input of inverter gate 2 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 4 | 2Y | output | Data output of inverter gate 2 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 5 | 3A | input | Data input of inverter gate 3 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 6 | 3Y | output | Data output of inverter gate 3 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 7 | GND | power_in | Ground (0 V) reference for all voltages in the device. |
| 8 | 4Y | output | Data output of inverter gate 4 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 9 | 4A | input | Data input of inverter gate 4 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 10 | 5Y | output | Data output of inverter gate 5 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 11 | 5A | input | Data input of inverter gate 5 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 12 | 6Y | output | Data output of inverter gate 6 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 13 | 6A | input | Data input of inverter gate 6 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 14 | VCC | power_in | Supply voltage; recommended range is 1.65 V to 3.6 V (functional down to 1.2 V). |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-14-EP(2.5x3) |
| Category | Logic |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage (absolute maximum) | VCC | -0.5 | 6.5 | V | 3 | ||
| input clamping current | IIK | -50 | mA | VI < 0 | 3 | ||
| input voltage (absolute maximum) | VI | -0.5 | 6.5 | V | 3 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 | 3 | |
| output voltage (absolute maximum) | VO | -0.5 | V | 3 | |||
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 3 | |
| supply current (absolute maximum) | ICC | 100 | mA | 3 | |||
| ground current | IGND | -100 | mA | 3 | |||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| supply voltage | VCC | 1.65 | 3.6 | V | 4 | ||
| supply voltage (functional) | VCC | 1.2 | V | functional | 4 | ||
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage | VO | 0 | V | 4 | |||
| ambient temperature | Tamb | -40 | 125 | °C | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 1.65 V to 2.7 V | 4 | |
| input transition rise and fall rate | Δt/ΔV | 0 | 10 | ns/V | VCC = 2.7 V to 3.6 V | 4 | |
| HIGH-level input voltage | VIH | 1.08 | V | VCC = 1.2 V; -40 °C to +125 °C | 4 | ||
| HIGH-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 4 | ||
| LOW-level input voltage | VIL | 0.12 | V | VCC = 1.2 V; -40 °C to +125 °C | 4 | ||
| LOW-level input voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 4 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 1.05 | V | VI = VIH or VIL; IO = -4 mA; VCC = 1.65 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 1.65 | V | VI = VIH or VIL; IO = -8 mA; VCC = 2.3 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.05 | V | VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 2.25 | V | VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 2 | V | VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.3 | V | VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.65 | V | VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.8 | V | VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.6 | V | VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V; -40 °C to +125 °C | 4 | ||
| input leakage current | II | -20 | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND; -40 °C to +125 °C | 5 | |
| supply current | ICC | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A; -40 °C to +125 °C | 5 | |
| additional supply current | ΔICC | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A; -40 °C to +125 °C | 5 | |
| propagation delay | tpd | 0.3 | 3.7 | 10.2 | ns | nA to nY; see Fig. 6; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C | 5 |
| propagation delay | tpd | 0.5 | 2.2 | 5.8 | ns | nA to nY; see Fig. 6; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 5 |
| propagation delay | tpd | 1 | 2.1 | 7 | ns | nA to nY; see Fig. 6; VCC = 2.7 V; -40 °C to +125 °C | 5 |
| propagation delay | tpd | 1 | 2 | 6 | ns | nA to nY; see Fig. 6; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 5 |
| output skew time | tsk(o) | 1.5 | ns | VCC = 3.0 V to 3.6 V; per buffer; VI = GND to VCC; -40 °C to +125 °C | 5 |
CAD (KiCad official)
- Symbol:
74LVC04ABQ - Footprint:
Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm - 3D model: DHVQFN-14-EP(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74lvc04abq-etched.step/74lvc04abq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc04abq.step/74lvc04abq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
111d1156e8fd41cd, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74LVC04ABQ
**Nexperia** · Inverters · DHVQFN-14-EP(2.5x3)
74LVC04ABQ from Nexperia, in a DHVQFN-14-EP(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverter gate 1 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 2 | 1Y | output | Data output of inverter gate 1 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 3 | 2A | input | Data input of inverter gate 2 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 4 | 2Y | output | Data output of inverter gate 2 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 5 | 3A | input | Data input of inverter gate 3 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 6 | 3Y | output | Data output of inverter gate 3 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 7 | GND | power_in | Ground (0 V) reference for all voltages in the device. |
| 8 | 4Y | output | Data output of inverter gate 4 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 9 | 4A | input | Data input of inverter gate 4 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 10 | 5Y | output | Data output of inverter gate 5 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 11 | 5A | input | Data input of inverter gate 5 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 12 | 6Y | output | Data output of inverter gate 6 (Y is the logical inverse of A: L input gives H output, H input gives L output). |
| 13 | 6A | input | Data input of inverter gate 6 with Schmitt-trigger action; recommended input voltage range is 0 V to 5.5 V. |
| 14 | VCC | power_in | Supply voltage; recommended range is 1.65 V to 3.6 V (functional down to 1.2 V). |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-14-EP(2.5x3) |
| Category | Logic |
| Pins | 15 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage (absolute maximum) | VCC | -0.5 | | 6.5 | V | | 3 |
| input clamping current | IIK | -50 | | | mA | VI < 0 | 3 |
| input voltage (absolute maximum) | VI | -0.5 | | 6.5 | V | | 3 |
| output clamping current | IOK | -50 | | 50 | mA | VO > VCC or VO < 0 | 3 |
| output voltage (absolute maximum) | VO | -0.5 | | | V | | 3 |
| output current | IO | -50 | | 50 | mA | VO = 0 V to VCC | 3 |
| supply current (absolute maximum) | ICC | | | 100 | mA | | 3 |
| ground current | IGND | -100 | | | mA | | 3 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| supply voltage | VCC | 1.65 | | 3.6 | V | | 4 |
| supply voltage (functional) | VCC | 1.2 | | | V | functional | 4 |
| input voltage | VI | 0 | | 5.5 | V | | 4 |
| output voltage | VO | 0 | | | V | | 4 |
| ambient temperature | Tamb | -40 | | 125 | °C | | 4 |
| input transition rise and fall rate | Δt/ΔV | 0 | | 20 | ns/V | VCC = 1.65 V to 2.7 V | 4 |
| input transition rise and fall rate | Δt/ΔV | 0 | | 10 | ns/V | VCC = 2.7 V to 3.6 V | 4 |
| HIGH-level input voltage | VIH | 1.08 | | | V | VCC = 1.2 V; -40 °C to +125 °C | 4 |
| HIGH-level input voltage | VIH | 1.7 | | | V | VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 4 |
| HIGH-level input voltage | VIH | 2 | | | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 4 |
| LOW-level input voltage | VIL | | | 0.12 | V | VCC = 1.2 V; -40 °C to +125 °C | 4 |
| LOW-level input voltage | VIL | | | 0.7 | V | VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 4 |
| LOW-level input voltage | VIL | | | 0.8 | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 1.05 | | | V | VI = VIH or VIL; IO = -4 mA; VCC = 1.65 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 1.65 | | | V | VI = VIH or VIL; IO = -8 mA; VCC = 2.3 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 2.05 | | | V | VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 2.25 | | | V | VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 2 | | | V | VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | | 0.3 | V | VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | | 0.65 | V | VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | | 0.8 | V | VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | | 0.6 | V | VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V; -40 °C to +125 °C | 4 |
| input leakage current | II | -20 | | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND; -40 °C to +125 °C | 5 |
| supply current | ICC | | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A; -40 °C to +125 °C | 5 |
| additional supply current | ΔICC | | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A; -40 °C to +125 °C | 5 |
| propagation delay | tpd | 0.3 | 3.7 | 10.2 | ns | nA to nY; see Fig. 6; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C | 5 |
| propagation delay | tpd | 0.5 | 2.2 | 5.8 | ns | nA to nY; see Fig. 6; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 5 |
| propagation delay | tpd | 1 | 2.1 | 7 | ns | nA to nY; see Fig. 6; VCC = 2.7 V; -40 °C to +125 °C | 5 |
| propagation delay | tpd | 1 | 2 | 6 | ns | nA to nY; see Fig. 6; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 5 |
| output skew time | tsk(o) | | | 1.5 | ns | VCC = 3.0 V to 3.6 V; per buffer; VI = GND to VCC; -40 °C to +125 °C | 5 |
## CAD (KiCad official)
- Symbol: `74LVC04ABQ`
- Footprint: `Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm`
- 3D model: DHVQFN-14-EP(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `74lvc04abq-etched.step` / `74lvc04abq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc04abq.step` / `74lvc04abq.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74LVC04ABQ.pdf) (12 pp, sha256 `111d1156e8fd41cd`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74lvc04abq-datasheet.pdf)