component
74LVC02AD
Public Made by Adomby adom
Nexperia Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LVC02AD
Nexperia · Logic Gates · SOIC-14
74LVC02AD from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Data output of gate 1 (NOR of 1A and 1B); output current limit is ±50 mA and output voltage ranges from 0 V to VCC. |
| 2 | 1A | input | Data input A of gate 1; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 3 | 1B | input | Data input B of gate 1; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 4 | 2Y | output | Data output of gate 2 (NOR of 2A and 2B); output current limit is ±50 mA and output voltage ranges from 0 V to VCC. |
| 5 | 2A | input | Data input A of gate 2; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 6 | 2B | input | Data input B of gate 2; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 7 | GND | power_in | Ground reference (0 V); all voltages in the datasheet are referenced to this pin. |
| 8 | 3A | input | Data input A of gate 3; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 9 | 3B | input | Data input B of gate 3; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 10 | 3Y | output | Data output of gate 3 (NOR of 3A and 3B); output current limit is ±50 mA and output voltage ranges from 0 V to VCC. |
| 11 | 4A | input | Data input A of gate 4; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 12 | 4B | input | Data input B of gate 4; overvoltage tolerant to 5.5 V with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 13 | 4Y | output | Data output of gate 4 (NOR of 4A and 4B); output current limit is ±50 mA and output voltage ranges from 0 V to VCC. |
| 14 | VCC | power_in | Supply voltage; recommended range is 1.65 V to 3.6 V (functional down to 1.2 V) with absolute maximum of 6.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| input voltage LOW-level, VCC = 1.2 V | VIL | 0.12 | V | VCC = 1.2 V | 4 | ||
| input voltage LOW-level, VCC = 2.3 V to 2.7 V | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| input voltage LOW-level, VCC = 2.7 V to 3.6 V | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| input voltage HIGH-level, VCC = 1.2 V | VIH | 1.08 | V | VCC = 1.2 V | 4 | ||
| input voltage HIGH-level, VCC = 2.3 V to 2.7 V | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| input voltage HIGH-level, VCC = 2.7 V to 3.6 V | VIH | 2 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| output voltage HIGH-level, VCC = 1.65 V | VOH | 1.05 | V | VI = VIH or VIL; IO = -4 mA; VCC = 1.65 V | 4 | ||
| output voltage HIGH-level, VCC = 2.3 V | VOH | 1.65 | V | VI = VIH or VIL; IO = -8 mA; VCC = 2.3 V | 4 | ||
| output voltage HIGH-level, VCC = 2.7 V | VOH | 2.05 | V | VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V | 4 | ||
| output voltage HIGH-level, VCC = 3.0 V (IO = -18 mA) | VOH | 2.25 | V | VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V | 4 | ||
| output voltage HIGH-level, VCC = 3.0 V (IO = -24 mA) | VOH | 2 | V | VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V | 4 | ||
| output voltage LOW-level, IO = 100 μA | VOL | 0.3 | V | VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V | 4 | ||
| output voltage LOW-level, VCC = 1.65 V | VOL | 0.65 | V | VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V | 4 | ||
| output voltage LOW-level, VCC = 2.3 V | VOL | 0.8 | V | VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V | 4 | ||
| output voltage LOW-level, VCC = 2.7 V | VOL | 0.6 | V | VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V | 4 | ||
| output voltage LOW-level, VCC = 3.0 V | VOL | 0.8 | V | VI = VIH or VIL; IO = 24 mA; VCC = 3.0 V | 4 | ||
| input leakage current | II | -20 | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND | 4 | |
| supply current | ICC | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 4 | |
| additional supply current per input pin | ΔICC | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 4 | |
| propagation delay, VCC = 1.65 V to 1.95 V | tpd | 0.5 | 4 | 10.1 | ns | VCC = 1.65 V to 1.95 V; nA, nB to nY; see Fig. 4 | 5 |
| propagation delay, VCC = 2.3 V to 2.7 V | tpd | 1 | 2.4 | 5.7 | ns | VCC = 2.3 V to 2.7 V; nA, nB to nY; see Fig. 4 | 5 |
| propagation delay, VCC = 2.7 V | tpd | 1 | 2.5 | 6.5 | ns | VCC = 2.7 V; nA, nB to nY; see Fig. 4 | 5 |
| propagation delay, VCC = 3.0 V to 3.6 V | tpd | 1 | 2.2 | 5.5 | ns | VCC = 3.0 V to 3.6 V; nA, nB to nY; see Fig. 4 | 5 |
| output skew time | tsk(o) | 1.5 | ns | VCC = 3.0 V to 3.6 V; per gate; VI = GND to VCC | 5 | ||
| supply voltage | VCC | 1.65 | 3.6 | V | 3 | ||
| supply voltage (functional) | VCC | 1.2 | V | functional | 3 | ||
| input voltage | VI | 0 | 5.5 | V | 3 | ||
| output voltage | VO | 0 | V | output HIGH or LOW state; upper limit printed as VCC | 3 | ||
| ambient temperature | Tamb | -40 | 125 | °C | 3 | ||
| input transition rise and fall rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 1.65 V to 2.7 V | 3 | |
| input transition rise and fall rate | Δt/ΔV | 0 | 10 | ns/V | VCC = 2.7 V to 3.6 V | 3 | |
| supply voltage | VCC | -0.5 | 6.5 | V | 3 | ||
| input clamping current | IIK | -50 | mA | VI < 0 V | 3 | ||
| input voltage | VI | -0.5 | 6.5 | V | 3 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 V | 3 | |
| output voltage | VO | -0.5 | V | output in HIGH or LOW-state; upper limit printed as VCC + 0.5 | 3 | ||
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 3 | |
| supply current | ICC | 100 | mA | 3 | |||
| ground current | IGND | -100 | mA | 3 | |||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| storage temperature | Tstg | -65 | 150 | °C | 3 |
CAD (KiCad official)
- Symbol:
74LVC02AD - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74lvc02ad-etched.step/74lvc02ad-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc02ad.step/74lvc02ad.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
5d712f94cef224bf, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).