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74LVC00AD

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Nexperia Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC00AD

Nexperia · Logic Gates · SOIC-14

74LVC00AD from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of NAND gate 1, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
2 1B input Data input 1B of NAND gate 1, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
3 1Y output Output 1Y of NAND gate 1; Y is LOW only when both 1A and 1B are HIGH.
4 2A input Data input 2A of NAND gate 2, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
5 2B input Data input 2B of NAND gate 2, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
6 2Y output Output 2Y of NAND gate 2; Y is LOW only when both 2A and 2B are HIGH.
7 GND power_in Ground (0 V); all voltages are referenced to this pin.
8 3Y output Output 3Y of NAND gate 3; Y is LOW only when both 3A and 3B are HIGH.
9 3A input Data input 3A of NAND gate 3, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
10 3B input Data input 3B of NAND gate 3, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
11 4Y output Output 4Y of NAND gate 4; Y is LOW only when both 4A and 4B are HIGH.
12 4A input Data input 4A of NAND gate 4, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
13 4B input Data input 4B of NAND gate 4, Schmitt-trigger input that is overvoltage tolerant to 5.5 V.
14 VCC power_in Supply voltage; the datasheet recommends 1.65 V to 3.6 V, functional down to 1.2 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 3
input clamping current IIK -50 mA VI < 0 V 3
input voltage VI -0.5 6.5 V 3
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 3
output voltage VO -0.5 V output in HIGH or LOW-state; max printed as VCC + 0.5 V 3
output current IO -50 50 mA VO = 0 V to VCC 3
supply current ICC 100 mA 3
ground current IGND -100 mA 3
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
storage temperature Tstg -65 150 °C 3
supply voltage VCC 1.65 3.6 V 3
supply voltage (functional) VCC 1.2 V functional 3
input voltage VI 0 5.5 V 3
output voltage VO 0 V output HIGH or LOW state; max printed as VCC 3
ambient temperature Tamb -40 125 °C 3
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 3
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 3
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 4
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 4
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 4
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 4
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 4
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 4
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 4
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 4
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 4
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 4
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 4
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 4
input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND 4
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 4
additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 4
propagation delay tpd 0.3 3.8 9.7 ns nA, nB to nY; see Fig. 4; VCC = 1.65 V to 1.95 V 5
propagation delay tpd 1 2.2 5.7 ns nA, nB to nY; see Fig. 4; VCC = 2.3 V to 2.7 V 5
propagation delay tpd 1 2.3 5.9 ns nA, nB to nY; see Fig. 4; VCC = 2.7 V 5
propagation delay tpd 0.5 2 5.1 ns nA, nB to nY; see Fig. 4; VCC = 3.0 V to 3.6 V 5
output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V; per gate; VI = GND to VCC 5
propagation delay tpd 12 ns nA, nB to nY; see Fig. 4; VCC = 1.2 V 5
input capacitance CI 4 pF VCC = 0 V to 3.6 V; VI = GND to VCC 4
power dissipation capacitance CPD 5.6 pF VCC = 1.65 V to 1.95 V 5
power dissipation capacitance CPD 8.9 pF VCC = 2.3 V to 2.7 V 5
power dissipation capacitance CPD 11.8 pF VCC = 3.0 V to 3.6 V 5

CAD (KiCad official)

  • Symbol: 74LVC00AD
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvc00ad-etched.step / 74lvc00ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc00ad.step / 74lvc00ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 1b2181291609fac9, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF