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74LVC00ABQ

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Nexperia Logic Gates, DHVQFN-14-EP(2.5x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC00ABQ

Nexperia · Logic Gates · DHVQFN-14-EP(2.5x3)

74LVC00ABQ from Nexperia, in a DHVQFN-14-EP(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of NAND gate 1; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
2 1B input Data input 1B of NAND gate 1; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
3 1Y output Data output 1Y of NAND gate 1 (1Y = NOT(1A AND 1B)); output must stay within 0 V to VCC.
4 2A input Data input 2A of NAND gate 2; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
5 2B input Data input 2B of NAND gate 2; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
6 2Y output Data output 2Y of NAND gate 2 (2Y = NOT(2A AND 2B)); output must stay within 0 V to VCC.
7 GND power_in Ground (0 V) reference for all voltages in the datasheet.
8 3Y output Data output 3Y of NAND gate 3 (3Y = NOT(3A AND 3B)); output must stay within 0 V to VCC.
9 3A input Data input 3A of NAND gate 3; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
10 3B input Data input 3B of NAND gate 3; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
11 4Y output Data output 4Y of NAND gate 4 (4Y = NOT(4A AND 4B)); output must stay within 0 V to VCC.
12 4A input Data input 4A of NAND gate 4; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
13 4B input Data input 4B of NAND gate 4; Schmitt-trigger input, overvoltage tolerant to 5.5 V, recommended input voltage 0 V to 5.5 V.
14 VCC power_in Supply voltage; recommended operating range 1.65 V to 3.6 V (functional down to 1.2 V).
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-14-EP(2.5x3)
Category Logic
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 1.65 3.6 V 3
supply voltage (functional) 1.2 V functional 3
input voltage VI 0 5.5 V 3
output voltage VO 0 V output HIGH or LOW state 3
ambient temperature Tamb -40 125 °C 3
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 3
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 3
supply voltage VCC -0.5 6.5 V 3
input clamping current IIK -50 mA VI < 0 V 3
input voltage VI -0.5 6.5 V 3
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 3
output voltage VO -0.5 V output in HIGH or LOW-state 3
output current IO -50 50 mA VO = 0 V to VCC 3
supply current ICC 100 mA 3
ground current IGND -100 mA 3
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
storage temperature Tstg -65 150 °C 3
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 4
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 4
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 4
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 4
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 4
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 4
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 4
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 4
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 4
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 4
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 4
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 4
input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND 4
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 4
additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 4
propagation delay nA, nB to nY tpd 0.3 3.8 9.7 ns nA, nB to nY; see Fig. 4; VCC = 1.65 V to 1.95 V 5
propagation delay nA, nB to nY tpd 1 2.2 5.7 ns nA, nB to nY; see Fig. 4; VCC = 2.3 V to 2.7 V 5
propagation delay nA, nB to nY tpd 1 2.3 5.9 ns nA, nB to nY; see Fig. 4; VCC = 2.7 V 5
propagation delay nA, nB to nY tpd 0.5 2 5.1 ns nA, nB to nY; see Fig. 4; VCC = 3.0 V to 3.6 V 5
output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V; per gate; VI = GND to VCC 5
propagation delay nA, nB to nY tpd 12 ns nA, nB to nY; see Fig. 4; VCC = 1.2 V 5
power dissipation capacitance CPD 5.6 pF VCC = 1.65 V to 1.95 V 5
power dissipation capacitance CPD 8.9 pF VCC = 2.3 V to 2.7 V 5
power dissipation capacitance CPD 11.8 pF VCC = 3.0 V to 3.6 V 5
input capacitance CI 4 pF VCC = 0 V to 3.6 V; VI = GND to VCC 4

CAD (KiCad official)

  • Symbol: 74LVC00ABQ
  • Footprint: Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm
  • 3D model: DHVQFN-14-EP(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74lvc00abq-etched.step / 74lvc00abq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc00abq.step / 74lvc00abq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 1b2181291609fac9, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF