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74LV74PW

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LV74PW

Nexperia · Flip Flops · TSSOP-14

74LV74PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1RD input Asynchronous reset-direct input (active-LOW) for flip-flop 1.
2 1D input Data input for flip-flop 1; data that meets the set-up and hold times on the LOW-to-HIGH clock transition is stored and appears at nQ.
3 1CP input Clock input for flip-flop 1, LOW-to-HIGH edge-triggered.
4 1SD input Asynchronous set-direct input (active-LOW) for flip-flop 1.
5 1Q output True flip-flop output 1Q.
6 ~{1Q} output Complement flip-flop output 1Q (complement of 1Q).
7 GND power_in Ground (0 V).
8 ~{2Q} output Complement flip-flop output 2Q (complement of 2Q).
9 2Q output True flip-flop output 2Q.
10 2SD input Asynchronous set-direct input (active-LOW) for flip-flop 2.
11 2CP input Clock input for flip-flop 2, LOW-to-HIGH edge-triggered.
12 2D input Data input for flip-flop 2; data that meets the set-up and hold times on the LOW-to-HIGH clock transition is stored and appears at nQ.
13 2RD input Asynchronous reset-direct input (active-LOW) for flip-flop 2.
14 VCC power_in Supply voltage, specified from 1.0 V to 5.5 V in the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 1 3.3 5.5 V 5
input voltage VI 0 V 5
output voltage VO 0 V 5
ambient temperature Tamb -40 125 °C 5
input transition rise and fall rate Δt/ΔV 0 500 ns/V VCC = 1.0 V to 2.0 V 5
input transition rise and fall rate Δt/ΔV 0 200 ns/V VCC = 2.0 V to 2.7 V 5
input transition rise and fall rate Δt/ΔV 0 100 ns/V VCC = 2.7 V to 3.6 V 5
input transition rise and fall rate Δt/ΔV 0 50 ns/V VCC = 3.6 V to 5.5 V 5
supply voltage VCC -0.5 7 V 4
input clamping current IIK 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
input voltage VI -0.5 7 V 4
output clamping current IOK -50 50 mA VO > VCC or VO < 0 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC -50 50 mA 4
ground current IGND -50 50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 Tamb = -40 °C to +125 °C 4
HIGH-level input voltage VIH 0.9 V VCC = 1.2 V 6
HIGH-level input voltage VIH 1.4 V VCC = 2.3 V to 2.7 V 6
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 6
LOW-level input voltage VIL 0.3 V VCC = 1.2 V 6
LOW-level input voltage VIL 0.6 V VCC = 2.3 V to 2.7 V 6
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 6
HIGH-level output voltage VOH 1.8 V VCC = 2.0 V; VI = VIH or VIL; IO = -100 μA 6
HIGH-level output voltage VOH 2.5 V VCC = 2.7 V; VI = VIH or VIL; IO = -100 μA 6
HIGH-level output voltage VOH 2.8 V VCC = 3.0 V; VI = VIH or VIL; IO = -100 μA 6
HIGH-level output voltage VOH 4.3 V VCC = 4.5 V; VI = VIH or VIL; IO = -100 μA 6
HIGH-level output voltage VOH 2.2 V VCC = 3.0 V; IO = -6 mA; standard outputs: VI = VIH or VIL 6
HIGH-level output voltage VOH 3.5 V VCC = 4.5 V; IO = -12 mA; standard outputs: VI = VIH or VIL 6
LOW-level output voltage VOL 0.2 V VCC = 2.0 V; VI = VIH or VIL; IO = 100 μA 6
LOW-level output voltage VOL 0.5 V VCC = 3.0 V; IO = 6 mA; standard outputs: VI = VIH or VIL 6
LOW-level output voltage VOL 0.65 V VCC = 4.5 V; IO = 12 mA; standard outputs: VI = VIH or VIL 6
input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V 6
supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 6
additional supply current ΔICC 850 μA VI = VCC, 0.6 V; VCC = 2.7 V to 3.6 V 6
propagation delay nCP to nQ, nQ tpd 56 ns VCC = 2.0 V; see Fig. 7 7
propagation delay nCP to nQ, nQ tpd 41 ns VCC = 2.7 V; see Fig. 7 7
propagation delay nCP to nQ, nQ tpd 33 ns VCC = 3.0 V to 3.6 V; see Fig. 7 7
propagation delay nCP to nQ, nQ tpd 23 ns VCC = 4.5 V to 5.5 V; see Fig. 7 7
pulse width nCP input HIGH to LOW tW 41 ns VCC = 2.0 V; see Fig. 7 7
pulse width nCP input HIGH to LOW tW 30 ns VCC = 2.7 V; see Fig. 7 7
pulse width nCP input HIGH to LOW tW 24 ns VCC = 3.0 V to 3.6 V; see Fig. 7 7
pulse width nCP input HIGH to LOW tW 18 ns VCC = 4.5 V to 5.5 V; see Fig. 7 7
set-up time nD to nCP tsu 26 ns VCC = 2.0 V; see Fig. 7 8
set-up time nD to nCP tsu 15 ns VCC = 2.7 V; see Fig. 7 8
set-up time nD to nCP tsu 10 ns VCC = 3.0 V to 3.6 V; see Fig. 7 8
set-up time nD to nCP tsu 8 ns VCC = 4.5 V to 5.5 V; see Fig. 7 8
hold time nD to nCP th 3 ns VCC = 2.0 V; see Fig. 7 8
maximum frequency nCP fmax 12 MHz VCC = 2.0 V; see Fig. 7 8
maximum frequency nCP fmax 40 MHz VCC = 2.7 V; see Fig. 7 8
maximum frequency nCP fmax 48 MHz VCC = 3.0 V to 3.6 V; see Fig. 7 8
maximum frequency nCP fmax 56 MHz VCC = 4.5 V to 5.5 V; see Fig. 7 8

CAD (KiCad official)

  • Symbol: 74LV74PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lv74pw-etched.step / 74lv74pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv74pw.step / 74lv74pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 223ddb283c012939, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF