component
74LV74D
Public Made by Adomby adom
Nexperia Flip Flops, SO-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LV74D
Nexperia · Flip Flops · SO-14
74LV74D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1RD | input | Asynchronous reset-direct input for flip-flop 1, active-LOW, which forces 1Q LOW and 1Q HIGH while asserted. |
| 2 | 1D | input | Data input for flip-flop 1, sampled on the LOW-to-HIGH clock transition, with set-up and hold times given in Table 7. |
| 3 | 1CP | input | Clock input for flip-flop 1, positive edge-triggered on the LOW-to-HIGH transition. |
| 4 | 1SD | input | Asynchronous set-direct input for flip-flop 1, active-LOW, which forces 1Q HIGH and 1Q LOW while asserted. |
| 5 | 1Q | output | True flip-flop output 1Q of flip-flop 1. |
| 6 | 1Q | output | Complement flip-flop output of flip-flop 1, the inverse of the true output on pin 5. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 2Q | output | Complement flip-flop output of flip-flop 2, the inverse of the true output on pin 9. |
| 9 | 2Q | output | True flip-flop output 2Q of flip-flop 2. |
| 10 | 2SD | input | Asynchronous set-direct input for flip-flop 2, active-LOW, which forces 2Q HIGH and 2Q LOW while asserted. |
| 11 | 2CP | input | Clock input for flip-flop 2, positive edge-triggered on the LOW-to-HIGH transition. |
| 12 | 2D | input | Data input for flip-flop 2, sampled on the LOW-to-HIGH clock transition, with set-up and hold times given in Table 7. |
| 13 | 2RD | input | Asynchronous reset-direct input for flip-flop 2, active-LOW, which forces 2Q LOW and 2Q HIGH while asserted. |
| 14 | VCC | power_in | Supply voltage, 1.0 V to 5.5 V per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | ||
| Input voltage | VI | -0.5 | 7 | V | 4 | ||
| Output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 | 4 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 | |
| Supply current | ICC | -50 | 50 | mA | 4 | ||
| Ground current | IGND | -50 | 50 | mA | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| Supply voltage | VCC | 1 | 3.3 | 5.5 | V | 5 | |
| Input voltage | VI | 0 | V | upper limit printed as VCC | 5 | ||
| Output voltage | VO | 0 | V | upper limit printed as VCC | 5 | ||
| Ambient temperature | Tamb | -40 | 125 | °C | 5 | ||
| Input transition rise and fall rate | Δt/ΔV | 0 | 500 | ns/V | VCC = 1.0 V to 2.0 V | 5 | |
| Input transition rise and fall rate | Δt/ΔV | 0 | 200 | ns/V | VCC = 2.0 V to 2.7 V | 5 | |
| Input transition rise and fall rate | Δt/ΔV | 0 | 100 | ns/V | VCC = 2.7 V to 3.6 V | 5 | |
| Input transition rise and fall rate | Δt/ΔV | 0 | 50 | ns/V | VCC = 3.6 V to 5.5 V | 5 | |
| HIGH-level input voltage | VIH | 0.9 | V | VCC = 1.2 V; -40 °C to +125 °C | 6 | ||
| HIGH-level input voltage | VIH | 1.4 | V | VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 6 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 6 | ||
| LOW-level input voltage | VIL | 0.3 | V | VCC = 1.2 V; -40 °C to +125 °C | 6 | ||
| LOW-level input voltage | VIL | 0.6 | V | VCC = 2.3 V to 2.7 V; -40 °C to +125 °C | 6 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 1.8 | V | VI = VIH or VIL; IO = -100 μA; VCC = 2.0 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 2.5 | V | VI = VIH or VIL; IO = -100 μA; VCC = 2.7 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 2.8 | V | VI = VIH or VIL; IO = -100 μA; VCC = 3.0 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 4.3 | V | VI = VIH or VIL; IO = -100 μA; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 2.2 | V | standard outputs: VI = VIH or VIL; VCC = 3.0 V; IO = -6 mA; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 3.5 | V | standard outputs: VI = VIH or VIL; VCC = 4.5 V; IO = -12 mA; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0.2 | V | VI = VIH or VIL; IO = 100 μA; VCC = 2.0 V; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0.5 | V | standard outputs: VI = VIH or VIL; VCC = 3.0 V; IO = 6 mA; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0.65 | V | standard outputs: VI = VIH or VIL; VCC = 4.5 V; IO = 12 mA; -40 °C to +125 °C | 6 | ||
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 5.5 V; -40 °C to +125 °C | 6 | |
| Supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 6 | ||
| Additional supply current | ΔICC | 850 | μA | VI = VCC, 0.6 V; VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 6 | ||
| Propagation delay nCP to nQ, nQ | tpd | 56 | ns | nCP to nQ, nQ; see Fig. 7; VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nCP to nQ, nQ | tpd | 41 | ns | nCP to nQ, nQ; see Fig. 7; VCC = 2.7 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nCP to nQ, nQ | tpd | 33 | ns | nCP to nQ, nQ; see Fig. 7; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nCP to nQ, nQ | tpd | 23 | ns | nCP to nQ, nQ; see Fig. 7; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nSD to nQ, nQ | tpd | 58 | ns | nSD to nQ, nQ; see Fig. 8; VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nSD to nQ, nQ | tpd | 43 | ns | nSD to nQ, nQ; see Fig. 8; VCC = 2.7 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nSD to nQ, nQ | tpd | 34 | ns | nSD to nQ, nQ; see Fig. 8; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nSD to nQ, nQ | tpd | 24 | ns | nSD to nQ, nQ; see Fig. 8; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nRD to nQ, nQ | tpd | 58 | ns | nRD to nQ, nQ; see Fig. 8; VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nRD to nQ, nQ | tpd | 43 | ns | nRD to nQ, nQ; see Fig. 8; VCC = 2.7 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nRD to nQ, nQ | tpd | 34 | ns | nRD to nQ, nQ; see Fig. 8; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 7 | ||
| Propagation delay nRD to nQ, nQ | tpd | 24 | ns | nRD to nQ, nQ; see Fig. 8; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 7 | ||
| Pulse width LOW nSD or nRD | tW | 41 | ns | nSD or nRD pulse width LOW; see Fig. 8; VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| Pulse width LOW nSD or nRD | tW | 30 | ns | nSD or nRD pulse width LOW; see Fig. 8; VCC = 2.7 V; -40 °C to +125 °C | 7 | ||
| Pulse width LOW nSD or nRD | tW | 24 | ns | nSD or nRD pulse width LOW; see Fig. 8; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 7 | ||
| Pulse width LOW nSD or nRD | tW | 18 | ns | nSD or nRD pulse width LOW; see Fig. 8; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 7 | ||
| Maximum frequency | fmax | 12 | MHz | nCP; see Fig. 7; VCC = 2.0 V; -40 °C to +125 °C | 8 | ||
| Maximum frequency | fmax | 40 | MHz | nCP; see Fig. 7; VCC = 2.7 V; -40 °C to +125 °C | 8 | ||
| Maximum frequency | fmax | 48 | MHz | nCP; see Fig. 7; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C | 8 | ||
| Maximum frequency | fmax | 56 | MHz | nCP; see Fig. 7; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 8 |
CAD (KiCad official)
- Symbol:
74LV74D - Footprint:
Adom_Gen:Nexperia_74 - 3D model: SO-14 (KiCad packages3D, STEP)
- 3D model files:
74lv74d-etched.step/74lv74d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lv74d.step/74lv74d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (15 pp, sha256
223ddb283c012939, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).