# 74LV595PW

**Nexperia** · Shift Registers · TSSOP-16

74LV595PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel data output Q1 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 2 | Q2 | tri_state | Parallel data output Q2 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 3 | Q3 | tri_state | Parallel data output Q3 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 4 | Q4 | tri_state | Parallel data output Q4 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 5 | Q5 | tri_state | Parallel data output Q5 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 6 | Q6 | tri_state | Parallel data output Q6 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 7 | Q7 | tri_state | Parallel data output Q7 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 8 | GND | power_in | Ground reference (0 V); all voltages in the datasheet are referenced to this pin. |
| 9 | Q7S | output | Serial data output from the end of the 8-stage shift register, used for cascading devices; it is a standard driver output rated up to 25 mA. |
| 10 | MR | input | Master reset input, active LOW; a LOW resets the shift register only, and the register contents are not changed by OE. |
| 11 | SHCP | input | Shift register clock input; data on DS is shifted into the shift register on each LOW-to-HIGH transition of SHCP. |
| 12 | STCP | input | Storage register clock input; the shift register contents are transferred to the storage register on each LOW-to-HIGH transition of STCP. |
| 13 | OE | input | Output enable input, active LOW; a HIGH forces Q0 to Q7 into the high-impedance OFF-state without changing the register contents. |
| 14 | DS | input | Serial data input to the shift register; it is sampled on SHCP with the setup and hold times given in the dynamic characteristics. |
| 15 | Q0 | tri_state | Parallel data output Q0 of the storage register; it goes to high impedance when OE is HIGH, and the parallel outputs are bus driver outputs rated up to 35 mA. |
| 16 | VCC | power_in | Supply voltage; recommended operating range is 1.0 V to 3.6 V, with an absolute maximum of 4.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `74LV595PW`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `74lv595pw-etched.step` / `74lv595pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lv595pw.step` / `74lv595pw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884868441264128) (17 pp, sha256 `7c0b925cf003104e`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lv595pw-datasheet.pdf)