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74LV595D

Public Made by Adom

by adom

Nexperia Registers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74LV595D

Nexperia · Registers · SO-16

74LV595D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output Q1; 3-state output that goes high-impedance OFF-state when OE is HIGH.
2 Q2 tri_state Parallel data output Q2; 3-state output that goes high-impedance OFF-state when OE is HIGH.
3 Q3 tri_state Parallel data output Q3; 3-state output that goes high-impedance OFF-state when OE is HIGH.
4 Q4 tri_state Parallel data output Q4; 3-state output that goes high-impedance OFF-state when OE is HIGH.
5 Q5 tri_state Parallel data output Q5; 3-state output that goes high-impedance OFF-state when OE is HIGH.
6 Q6 tri_state Parallel data output Q6; 3-state output that goes high-impedance OFF-state when OE is HIGH.
7 Q7 tri_state Parallel data output Q7; 3-state output that goes high-impedance OFF-state when OE is HIGH.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 Q7S output Serial data output for cascading devices, showing the previous state of internal stage 6 on a shift.
10 MR input Master reset input, active LOW; a LOW resets the shift register.
11 SHCP input Shift register clock input; data is shifted on LOW-to-HIGH transitions.
12 STCP input Storage register clock input; a LOW-to-HIGH transition transfers the shift register contents to the storage register.
13 OE input Output enable input, active LOW; a HIGH forces the parallel outputs to the high-impedance OFF-state.
14 DS input Serial data input to the shift register; clamp diodes allow current-limited interface to voltages above VCC.
15 Q0 tri_state Parallel data output Q0; 3-state output that goes high-impedance OFF-state when OE is HIGH.
16 VCC power_in Supply voltage; recommended range 1.0 V to 3.6 V with absolute maximum rating of +4.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SO-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 4.6 V 5
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
output clamping current IOK -50 50 mA VI < -0.5 V or VI > VCC + 0.5 V 5
output current IO 25 mA -0.5 V < VO < VCC + 0.5 V; standard driver outputs 5
output current IO 35 mA -0.5 V < VO < VCC + 0.5 V; bus driver outputs 5
supply current ICC 50 mA standard driver outputs 5
supply current ICC 70 mA bus driver outputs 5
ground current IGND -50 mA standard driver outputs 5
ground current IGND -70 mA bus driver outputs 5
storage temperature Tstg -65 150 °C 5
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
supply voltage VCC 1 3.3 3.6 V 6
input voltage VI 0 V 6
output voltage VO 0 V 6
ambient temperature Tamb -40 125 °C 6
input transition rise and fall rate Δt/ΔV 500 ns/V VCC = 1.0 V to 2.0 V 6
input transition rise and fall rate Δt/ΔV 200 ns/V VCC = 2.0 V to 2.7 V 6
input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 2.7 V to 3.6 V 6
HIGH-level input voltage VIH 0.9 V VCC = 1.2 V 6
HIGH-level input voltage VIH 1.4 V VCC = 2.0 V 6
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 6
LOW-level input voltage VIL 0.3 V VCC = 1.2 V 6
LOW-level input voltage VIL 0.6 V VCC = 2.0 V 6
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 6
HIGH-level output voltage VOH 1.8 2 V all outputs; VI = VIH or VIL; IO = -100 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 2.5 2.7 V all outputs; VI = VIH or VIL; IO = -100 μA; VCC = 2.7 V 6
HIGH-level output voltage VOH 2.8 3 V all outputs; VI = VIH or VIL; IO = -100 μA; VCC = 3.0 V 6
HIGH-level output voltage VOH 2.2 2.82 V standard outputs; VI = VIH or VIL; IO = -6 mA; VCC = 3.0 V 6
LOW-level output voltage VOL 0 0.2 V all outputs; VI = VIH or VIL; IO = 100 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.25 0.5 V standard driver outputs VCC = 3.0 V; IO = 6 mA 6
LOW-level output voltage VOL 0.2 0.5 V bus driver outputs VCC = 3.0 V; IO = 8 mA 6
input leakage current II 1 μA VCC = 3.6 V; VI = 5.5 V or GND 6
OFF-state output current IOZ 10 μA VI = VIH or VIL; VO = VCC or GND; VCC = 3.6 V 7
supply current ICC 160 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 7
additional supply current ΔICC 850 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V 7
propagation delay SHCP to Q7S tpd 32 75 ns SHCP to Q7S; see Fig. 8; VCC = 2.0 V 7
propagation delay SHCP to Q7S tpd 24 55 ns SHCP to Q7S; see Fig. 8; VCC = 2.7 V 7
propagation delay SHCP to Q7S tpd 18 44 ns SHCP to Q7S; see Fig. 8; VCC = 3.0 V to 3.6 V 7
propagation delay STCP to Qn tpd 34 77 ns STCP to Qn; see Fig. 9; VCC = 2.0 V 7
propagation delay STCP to Qn tpd 25 56 ns STCP to Qn; see Fig. 9; VCC = 2.7 V 7
propagation delay STCP to Qn tpd 19 45 ns STCP to Qn; see Fig. 9; VCC = 3.0 V to 3.6 V 7
enable time OE to Qn ten 29 66 ns OE to Qn; see Fig. 12; VCC = 2.0 V 7
enable time OE to Qn ten 21 49 ns OE to Qn; see Fig. 12; VCC = 2.7 V 7
enable time OE to Qn ten 16 39 ns OE to Qn; see Fig. 12; VCC = 3.0 V to 3.6 V 7
SHCP pulse width HIGH or LOW tW 41 10 ns SHCP HIGH or LOW; see Fig. 8; VCC = 2.0 V 8
SHCP pulse width HIGH or LOW tW 30 8 ns SHCP HIGH or LOW; see Fig. 8; VCC = 2.7 V 8
SHCP pulse width HIGH or LOW tW 24 6 ns SHCP HIGH or LOW; see Fig. 8; VCC = 3.0 V to 3.6 V 8
STCP pulse width HIGH or LOW tW 41 7 ns STCP HIGH or LOW; see Fig. 9; VCC = 2.0 V 8
STCP pulse width HIGH or LOW tW 30 5 ns STCP HIGH or LOW; see Fig. 9; VCC = 2.7 V 8
STCP pulse width HIGH or LOW tW 24 4 ns STCP HIGH or LOW; see Fig. 9; VCC = 3.0 V to 3.6 V 8
set-up time DS to SHCP tsu 31 14 ns DS to SHCP; see Fig. 10; VCC = 2.0 V 8
set-up time DS to SHCP tsu 23 10 ns DS to SHCP; see Fig. 10; VCC = 2.7 V 8
set-up time DS to SHCP tsu 18 8 ns DS to SHCP; see Fig. 10; VCC = 3.0 V to 3.6 V 8
maximum frequency SHCP or STCP fmax 12 40 MHz SHCP or STCP; see Fig. 8 and Fig. 9; VCC = 2.0 V 8
maximum frequency SHCP or STCP fmax 16 58 MHz SHCP or STCP; see Fig. 8 and Fig. 9; VCC = 2.7 V 8
maximum frequency SHCP or STCP fmax 20 70 MHz SHCP or STCP; see Fig. 8 and Fig. 9; VCC = 3.0 V to 3.6 V 8

CAD (KiCad official)

  • Symbol: 74LV595D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SO-16 (KiCad packages3D, STEP)
  • 3D model files: 74lv595d-etched.step / 74lv595d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv595d.step / 74lv595d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 7c0b925cf003104e, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF