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74LV4060PW

Public Made by Adom

by adom

Nexperia Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LV4060PW

Nexperia · Counters, Dividers · TSSOP-16

74LV4060PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q11 output Buffered counter output Q11 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
2 Q12 output Buffered counter output Q12 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
3 Q13 output Buffered counter output Q13 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
4 Q5 output Buffered counter output Q5 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
5 Q4 output Buffered counter output Q4 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
6 Q6 output Buffered counter output Q6 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
7 Q3 output Buffered counter output Q3 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 CTC passive External capacitor connection for the RC/crystal oscillator; keep floating when the oscillator is bypassed by an external clock at RS, and Ct must be larger than stray capacitance.
10 RTC passive External resistor connection for the RC oscillator; keep floating when the oscillator is bypassed by an external clock at RS, and Rt should be between 10 kΩ and 1 MΩ with Rt ≥ 1 kΩ to avoid start-up problems.
11 RS input Clock input/oscillator pin; the counter advances on the HIGH-to-LOW transition of RS, and it may be driven by an external clock in place of the oscillator.
12 MR input Master reset; a HIGH level clears all counter stages and forces all outputs LOW, independent of the other input conditions.
13 Q8 output Buffered counter output Q8 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
14 Q7 output Buffered counter output Q7 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
15 Q9 output Buffered counter output Q9 of the 14-stage binary counter; forced LOW by a HIGH level on MR.
16 VCC power_in Supply voltage; recommended range 1.0 V to 5.5 V, with the part guaranteed to function down to 1.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -50 50 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage VCC 1 3.3 5.5 V 5
input voltage VI 0 V 5
output voltage VO 0 V 5
ambient temperature Tamb -40 125 °C in free air 5
input transition rise and fall rate Δt/ΔV 500 ns/V VCC = 1.0 V to 2.0 V 5
input transition rise and fall rate Δt/ΔV 200 ns/V VCC = 2.0 V to 2.7 V 5
input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 2.7 V to 3.6 V 5
input transition rise and fall rate Δt/ΔV 50 ns/V VCC = 3.6 V to 5.5 V 5
HIGH-level input voltage VIH 0.9 V MR input; VCC = 1.2 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 1.4 V MR input; VCC = 2.0 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 2 V MR input; VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 1 V RS input; VCC = 1.2 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 1.6 V RS input; VCC = 2.0 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 2.4 V RS input; VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.3 V MR input; VCC = 1.2 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.6 V MR input; VCC = 2.0 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.8 V MR input; VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.2 V RS input; VCC = 1.2 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.4 V RS input; VCC = 2.0 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.5 V RS input; VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 5
input leakage current II 1 μA VCC = 5.5 V; VI = VCC or GND; -40 °C to +125 °C 7
supply current ICC 20 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A; -40 °C to +85 °C 7
supply current ICC 160 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A; -40 °C to +125 °C 7
supply current ICC 80 μA VCC = 5.5 V; VI = VCC or GND; IO = 0 A; -40 °C to +125 °C 7
additional supply current ΔICC 500 μA VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A; -40 °C to +85 °C 7
additional supply current ΔICC 850 μA VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A; -40 °C to +125 °C 7
HIGH-level output voltage VOH 2.4 2.82 V RTC output; RS = MR = GND; VCC = 3.0 V; IO = -3.4 mA; -40 °C to +85 °C 6
HIGH-level output voltage VOH 2.2 V RTC output; RS = MR = GND; VCC = 3.0 V; IO = -3.4 mA; -40 °C to +125 °C 6
HIGH-level output voltage VOH 2.8 3 V RTC output; RS = MR = GND; VCC = 3.0 V; IO = -100 μA; -40 °C to +125 °C 6
LOW-level output voltage VOL 0.25 0.4 V RTC output; RS = VCC and MR = GND; VCC = 3.0 V; IO = -3.4 mA; -40 °C to +85 °C 7
LOW-level output voltage VOL 0.5 V RTC output; RS = VCC and MR = GND; VCC = 3.0 V; IO = -3.4 mA; -40 °C to +125 °C 7
LOW-level output voltage VOL 0 0.2 V RTC output; RS = VCC and MR = GND; VCC = 3.0 V; IO = -100 μA; -40 °C to +125 °C 7
propagation delay RS to Q3 tpd 33 53 ns VCC = 3.0 V to 3.6 V; -40 °C to +85 °C 8
propagation delay RS to Q3 tpd 66 ns VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 8
propagation delay RS to Q3 tpd 24 39 ns VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 8
propagation delay RS to Q3 tpd 49 ns VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 8
maximum frequency fmax 24 90 MHz VCC = 3.0 V to 3.6 V; -40 °C to +85 °C 9
maximum frequency fmax 15 MHz VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 9
maximum frequency fmax 30 100 MHz VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 9
maximum frequency fmax 19 MHz VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 9
HIGH to LOW propagation delay MR to Qn tPHL 19 31 ns VCC = 3.0 V to 3.6 V; -40 °C to +85 °C 8

CAD (KiCad official)

  • Symbol: 74LV4060PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74lv4060pw-etched.step / 74lv4060pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv4060pw.step / 74lv4060pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 30030905b6f3d180, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF