component
74LV4052PW
Public Made by Adomby adom
Nexperia Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdown74LV4052PW
Nexperia · Analog Switches, Multiplexers · TSSOP-16
74LV4052PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 2Y0 | passive | Independent input or output channel 0 of switch 2, connected to common terminal 2Z when E is LOW, S1 is LOW and S0 is LOW. |
| 2 | 2Y2 | passive | Independent input or output channel 2 of switch 2, connected to common terminal 2Z when E is LOW, S1 is HIGH and S0 is LOW. |
| 3 | 2Z | passive | Common input or output of switch 2, connected to the selected 2Yn channel when E is LOW. |
| 4 | 2Y3 | passive | Independent input or output channel 3 of switch 2, connected to common terminal 2Z when E is LOW, S1 is HIGH and S0 is HIGH. |
| 5 | 2Y1 | passive | Independent input or output channel 1 of switch 2, connected to common terminal 2Z when E is LOW, S1 is LOW and S0 is HIGH. |
| 6 | E | input | Enable input (active LOW); when HIGH, the switches are turned off. |
| 7 | VEE | power_in | Negative supply voltage. |
| 8 | GND | power_in | Ground (0 V). |
| 9 | S1 | input | Select logic input; together with S0 it chooses which nYn channel connects to nZ as given in the function table. |
| 10 | S0 | input | Select logic input; together with S1 it chooses which nYn channel connects to nZ as given in the function table. |
| 11 | 1Y3 | passive | Independent input or output channel 3 of switch 1, connected to common terminal 1Z when E is LOW, S1 is HIGH and S0 is HIGH. |
| 12 | 1Y0 | passive | Independent input or output channel 0 of switch 1, connected to common terminal 1Z when E is LOW, S1 is LOW and S0 is LOW. |
| 13 | 1Z | passive | Common input or output of switch 1, connected to the selected 1Yn channel when E is LOW. |
| 14 | 1Y1 | passive | Independent input or output channel 1 of switch 1, connected to common terminal 1Z when E is LOW, S1 is LOW and S0 is HIGH. |
| 15 | 1Y2 | passive | Independent input or output channel 2 of switch 1, connected to common terminal 1Z when E is LOW, S1 is HIGH and S0 is LOW. |
| 16 | VCC | power_in | Positive supply voltage; recommended operating range is 1 V to 6 V (Table 5). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| switch clamping current | ISK | -20 | 20 | mA | VSW < -0.5 V or VSW > VCC + 0.5 V | 4 | |
| switch current | ISW | -25 | 25 | mA | VSW > -0.5 V or VSW < VCC + 0.5 V; source or sink current | 4 | |
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| supply voltage | VCC | 1 | 3.3 | 6 | V | see Fig. 5 | 4 |
| ambient temperature | Tamb | -40 | 125 | °C | in free air | 4 | |
| input transition rise and fall rate | Δt/ΔV | 500 | ns/V | VCC = 1.0 V to 2.0 V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 200 | ns/V | VCC = 2.0 V to 2.7 V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 2.7 V to 6.0 V | 4 | ||
| HIGH-level input voltage | VIH | 0.9 | V | VCC = 1.2 V; -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage | VIH | 1.4 | V | VCC = 2.0 V; -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC = 4.5 V; -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| LOW-level input voltage | VIL | 0.3 | V | VCC = 1.2 V; -40 °C to +125 °C | 5 | ||
| LOW-level input voltage | VIL | 0.6 | V | VCC = 2.0 V; -40 °C to +125 °C | 5 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 5 | ||
| LOW-level input voltage | VIL | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C | 5 | ||
| LOW-level input voltage | VIL | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| input leakage current | II | 1 | μA | VI = VCC or GND; VCC = 3.6 V; -40 °C to +125 °C | 5 | ||
| input leakage current | II | 2 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| OFF-state leakage current | IS(OFF) | 1 | μA | VI = VIH or VIL; see Fig. 6; VCC = 3.6 V; -40 °C to +125 °C | 5 | ||
| OFF-state leakage current | IS(OFF) | 2 | μA | VI = VIH or VIL; see Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| ON-state leakage current | IS(ON) | 1 | μA | VI = VIH or VIL; see Fig. 7; VCC = 3.6 V; -40 °C to +125 °C | 5 | ||
| ON-state leakage current | IS(ON) | 2 | μA | VI = VIH or VIL; see Fig. 7; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 3.6 V; -40 °C to +125 °C | 5 | ||
| supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| additional supply current | ΔICC | 850 | μA | per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V; -40 °C to +125 °C | 5 | ||
| ON resistance (peak) | RON(peak) | 145 | 375 | Ω | VI = 0 V to VCC - VEE; VCC = 2.0 V; ISW = 1000 μA | 6 | |
| ON resistance (peak) | RON(peak) | 90 | 235 | Ω | VI = 0 V to VCC - VEE; VCC = 2.7 V; ISW = 1000 μA | 6 | |
| ON resistance (peak) | RON(peak) | 80 | 210 | Ω | VI = 0 V to VCC - VEE; VCC = 3.0 V to 3.6 V; ISW = 1000 μA | 6 | |
| ON resistance (peak) | RON(peak) | 60 | 160 | Ω | VI = 0 V to VCC - VEE; VCC = 4.5 V; ISW = 1000 μA | 6 | |
| ON resistance (peak) | RON(peak) | 55 | 145 | Ω | VI = 0 V to VCC - VEE; VCC = 6.0 V; ISW = 1000 μA | 6 | |
| ON resistance (rail) | RON(rail) | 110 | 270 | Ω | VI = GND; VCC = 2.0 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 70 | 165 | Ω | VI = GND; VCC = 2.7 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 60 | 150 | Ω | VI = GND; VCC = 3.0 V to 3.6 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 45 | 115 | Ω | VI = GND; VCC = 4.5 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 40 | 100 | Ω | VI = GND; VCC = 6.0 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 120 | 370 | Ω | VI = VCC - VEE; VCC = 2.0 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 75 | 225 | Ω | VI = VCC - VEE; VCC = 2.7 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 70 | 205 | Ω | VI = VCC - VEE; VCC = 3.0 V to 3.6 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 50 | 150 | Ω | VI = VCC - VEE; VCC = 4.5 V; ISW = 1000 μA | 7 | |
| ON resistance (rail) | RON(rail) | 45 | 135 | Ω | VI = VCC - VEE; VCC = 6.0 V; ISW = 1000 μA | 7 | |
| propagation delay | tpd | 9 | 20 | ns | nYn to nZ, nZ to nYn; see Fig. 10; VCC = 2.0 V | 8 | |
| propagation delay | tpd | 6 | 15 | ns | nYn to nZ, nZ to nYn; see Fig. 10; VCC = 2.7 V | 8 | |
| propagation delay | tpd | 5 | 12 | ns | nYn to nZ, nZ to nYn; see Fig. 10; VCC = 3.0 V to 3.6 V | 8 | |
| propagation delay | tpd | 4 | 10 | ns | nYn to nZ, nZ to nYn; see Fig. 10; VCC = 4.5 V | 8 | |
| propagation delay | tpd | 3 | 8 | ns | nYn to nZ, nZ to nYn; see Fig. 10; VCC = 6.0 V | 8 | |
| enable time | ten | 65 | 146 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 2.0 V | 8 | |
| enable time | ten | 48 | 108 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 2.7 V | 8 | |
| enable time | ten | 36 | 86 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 3.0 V to 3.6 V | 8 | |
| enable time | ten | 32 | 73 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 4.5 V | 8 | |
| enable time | ten | 25 | 56 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 6.0 V | 8 | |
| disable time | tdis | 43 | 95 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 2.0 V | 8 | |
| disable time | tdis | 33 | 71 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 2.7 V | 8 | |
| disable time | tdis | 26 | 57 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 3.0 V to 3.6 V | 8 | |
| disable time | tdis | 23 | 49 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 4.5 V | 8 | |
| disable time | tdis | 18 | 38 | ns | E, Sn to nYn, nZ; see Fig. 11; VCC = 6.0 V | 8 |
CAD (KiCad official)
- Symbol:
74LV4052PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74lv4052pw-etched.step/74lv4052pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lv4052pw.step/74lv4052pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (18 pp, sha256
dadae11c2492ccc7, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).