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74LV4051D

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Nexperia Analog Switches, Multiplexers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LV4051D

Nexperia · Analog Switches, Multiplexers · SO-16

74LV4051D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y4 passive Independent analog input/output Y4; it connects to common terminal Z when E is LOW and S2:S0 = 100, and is high-impedance when E is HIGH.
2 Y6 passive Independent analog input/output Y6; it connects to common terminal Z when E is LOW and S2:S0 = 110, and is high-impedance when E is HIGH.
3 Z passive Common analog input/output Z; its voltage may not exceed VCC or VEE, and it connects to the selected Yn channel when E is LOW.
4 Y7 passive Independent analog input/output Y7; it connects to common terminal Z when E is LOW and S2:S0 = 111, and is high-impedance when E is HIGH.
5 Y5 passive Independent analog input/output Y5; it connects to common terminal Z when E is LOW and S2:S0 = 101, and is high-impedance when E is HIGH.
6 E input Enable input (active LOW); when HIGH, all switches are in the high-impedance OFF-state independent of S0 to S2.
7 VEE power_in Supply voltage for the analog switch negative limit; VCC − VEE may not exceed 6.0 V, and VEE is connected to GND for digital multiplexer/demultiplexer operation.
8 GND power_in Ground supply voltage (0 V reference); VCC to GND range is 1.0 V to 6.0 V.
9 S2 input Select input S2 (most significant bit of the channel select code) for choosing one of eight channels when E is LOW.
10 S1 input Select input S1 for choosing one of eight channels when E is LOW.
11 S0 input Select input S0 (least significant bit of the channel select code) for choosing one of eight channels when E is LOW.
12 Y3 passive Independent analog input/output Y3; it connects to common terminal Z when E is LOW and S2:S0 = 011, and is high-impedance when E is HIGH.
13 Y0 passive Independent analog input/output Y0; it connects to common terminal Z when E is LOW and S2:S0 = 000, and is high-impedance when E is HIGH.
14 Y1 passive Independent analog input/output Y1; it connects to common terminal Z when E is LOW and S2:S0 = 001, and is high-impedance when E is HIGH.
15 Y2 passive Independent analog input/output Y2; it connects to common terminal Z when E is LOW and S2:S0 = 010, and is high-impedance when E is HIGH.
16 VCC power_in Supply voltage for digital control inputs S0 to S2 and E; the VCC to GND range is 1.0 V to 6.0 V, with an absolute maximum of 7.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SO-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 1 3.3 6 V see Fig. 5 5
ambient temperature Tamb -40 125 °C in free air 5
input transition rise and fall rate Δt/ΔV 500 ns/V VCC = 1.0 V to 2.0 V 5
input transition rise and fall rate Δt/ΔV 200 ns/V VCC = 2.0 V to 2.7 V 5
input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 2.7 V to 3.6 V 5
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
switch clamping current ISK -20 20 mA VSW < -0.5 V or VSW > VCC + 0.5 V 4
switch current ISW -25 25 mA VSW > -0.5 V or VSW < VCC + 0.5 V; source or sink current 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
HIGH-level input voltage VIH 0.9 V VCC = 1.2 V 5
HIGH-level input voltage VIH 1.4 V VCC = 2.0 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
HIGH-level input voltage VIH 3.15 V VCC = 4.5 V 5
HIGH-level input voltage VIH 4.2 V VCC = 6.0 V 5
LOW-level input voltage VIL 0.3 V VCC = 1.2 V 5
LOW-level input voltage VIL 0.6 V VCC = 2.0 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 1.35 V VCC = 4.5 V 5
LOW-level input voltage VIL 1.8 V VCC = 6.0 V 5
input leakage current II 1 μA VI = VCC or GND; VCC = 3.6 V 6
input leakage current II 2 μA VI = VCC or GND; VCC = 6.0 V 6
OFF-state leakage current IS(OFF) 1 μA VI = VIH or VIL; see Fig. 6; VCC = 3.6 V 6
OFF-state leakage current IS(OFF) 2 μA VI = VIH or VIL; see Fig. 6; VCC = 6.0 V 6
ON-state leakage current IS(ON) 1 μA VI = VIH or VIL; see Fig. 7; VCC = 3.6 V 6
ON-state leakage current IS(ON) 2 μA VI = VIH or VIL; see Fig. 7; VCC = 6.0 V 6
supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 3.6 V 6
supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 6
additional supply current per input ΔICC 850 μA VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V 6
ON resistance (peak) RON(peak) 145 375 Ω VI = 0 V to VCC - VEE; VCC = 2.0 V; ISW = 1000 μA 7
ON resistance (peak) RON(peak) 90 235 Ω VI = 0 V to VCC - VEE; VCC = 2.7 V; ISW = 1000 μA 7
ON resistance (peak) RON(peak) 80 210 Ω VI = 0 V to VCC - VEE; VCC = 3.0 V to 3.6 V; ISW = 1000 μA 7
ON resistance (peak) RON(peak) 60 160 Ω VI = 0 V to VCC - VEE; VCC = 4.5 V; ISW = 1000 μA 7
ON resistance (peak) RON(peak) 55 145 Ω VI = 0 V to VCC - VEE; VCC = 6.0 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 110 270 Ω VI = GND; VCC = 2.0 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 70 165 Ω VI = GND; VCC = 2.7 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 60 150 Ω VI = GND; VCC = 3.0 V to 3.6 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 45 115 Ω VI = GND; VCC = 4.5 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 40 100 Ω VI = GND; VCC = 6.0 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 120 370 Ω VI = VCC - VEE; VCC = 2.0 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 75 225 Ω VI = VCC - VEE; VCC = 2.7 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 70 205 Ω VI = VCC - VEE; VCC = 3.0 V to 3.6 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 50 150 Ω VI = VCC - VEE; VCC = 4.5 V; ISW = 1000 μA 7
ON resistance (rail) RON(rail) 45 135 Ω VI = VCC - VEE; VCC = 6.0 V; ISW = 1000 μA 7
propagation delay tpd 9 20 ns Yn to Z, Z to Yn; see Fig. 10; VCC = 2.0 V 8
propagation delay tpd 6 15 ns Yn to Z, Z to Yn; see Fig. 10; VCC = 2.7 V 8
propagation delay tpd 5 12 ns Yn to Z, Z to Yn; see Fig. 10; VCC = 3.0 V to 3.6 V 8
propagation delay tpd 4 10 ns Yn to Z, Z to Yn; see Fig. 10; VCC = 4.5 V 8
propagation delay tpd 3 8 ns Yn to Z, Z to Yn; see Fig. 10; VCC = 6.0 V 8
enable time ten 49 112 ns E to Yn, Z; see Fig. 11; VCC = 2.0 V 9
enable time ten 36 83 ns E to Yn, Z; see Fig. 11; VCC = 2.7 V 9
enable time ten 28 66 ns E to Yn, Z; see Fig. 11; VCC = 3.0 V to 3.6 V 9
enable time ten 25 56 ns E to Yn, Z; see Fig. 11; VCC = 4.5 V 9
enable time ten 19 43 ns E to Yn, Z; see Fig. 11; VCC = 6.0 V 9
disable time tdis 51 110 ns E to Yn, Z; see Fig. 11; VCC = 2.0 V 9
disable time tdis 38 82 ns E to Yn, Z; see Fig. 11; VCC = 2.7 V 9
disable time tdis 30 66 ns E to Yn, Z; see Fig. 11; VCC = 3.0 V to 3.6 V 9
disable time tdis 29 56 ns E to Yn, Z; see Fig. 11; VCC = 4.5 V 9
disable time tdis 21 44 ns E to Yn, Z; see Fig. 11; VCC = 6.0 V 9

CAD (KiCad official)

  • Symbol: 74LV4051D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SO-16 (KiCad packages3D, STEP)
  • 3D model files: 74lv4051d-etched.step / 74lv4051d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv4051d.step / 74lv4051d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (20 pp, sha256 64ed2ba45bb2edc3, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF