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74LV165PW

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Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LV165PW

Nexperia · Shift Registers · TSSOP-16

74LV165PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL input Parallel enable input, active LOW: when LOW, D0 to D7 are loaded into the register asynchronously, and when HIGH, data enters serially at DS.
2 CP input Clock input, LOW-to-HIGH edge-triggered, shifts data when CE is LOW.
3 D4 input Parallel data input D4, loaded asynchronously when PL is LOW.
4 D5 input Parallel data input D5, loaded asynchronously when PL is LOW.
5 D6 input Parallel data input D6, loaded asynchronously when PL is LOW.
6 D7 input Parallel data input D7, loaded asynchronously when PL is LOW.
7 Q7 output Complementary serial output from the last stage.
8 GND power_in Ground (0 V) reference for all voltages.
9 Q7 output Serial output from the last stage.
10 DS input Serial data input, shifted into the register on the LOW-to-HIGH CP edge when PL is HIGH and CE is LOW.
11 D0 input Parallel data input D0, loaded asynchronously when PL is LOW.
12 D1 input Parallel data input D1, loaded asynchronously when PL is LOW.
13 D2 input Parallel data input D2, loaded asynchronously when PL is LOW.
14 D3 input Parallel data input D3, loaded asynchronously when PL is LOW.
15 CE input Clock enable input, active LOW; a HIGH on CE disables the CP input.
16 VCC power_in Positive supply voltage, recommended operating range 1.0 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC 1 3.3 5.5 V 5
Ambient temperature Tamb -40 125 °C 5
Input transition rise and fall rate Δt/ΔV 0 500 ns/V VCC = 1.0 V to 2.0 V 5
Input transition rise and fall rate Δt/ΔV 0 200 ns/V VCC = 2.0 V to 2.7 V 5
Input transition rise and fall rate Δt/ΔV 0 100 ns/V VCC = 2.7 V to 3.6 V 5
Input transition rise and fall rate Δt/ΔV 0 50 ns/V VCC = 3.6 V to 5.5 V 5
Supply voltage VCC -0.5 7 V 5
Input clamping current IIK -20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
Input voltage VI -0.5 7 V 5
Output clamping current IOK -50 50 mA VO > VCC or VO < 0 5
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 5
Supply current ICC 50 mA 5
Ground current IGND -50 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
HIGH-level input voltage VIH 0.9 V VCC = 1.2 V 6
HIGH-level input voltage VIH 1.4 V VCC = 2.3 V to 2.7 V 6
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 6
LOW-level input voltage VIL 0.3 V VCC = 1.2 V 6
LOW-level input voltage VIL 0.6 V VCC = 2.3 V to 2.7 V 6
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 6
HIGH-level output voltage VOH 1.8 V VI = VIH or VIL; IO = -100 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 2.5 V VI = VIH or VIL; IO = -100 μA; VCC = 2.7 V 6
HIGH-level output voltage VOH 2.8 V VI = VIH or VIL; IO = -100 μA; VCC = 3.0 V 6
HIGH-level output voltage VOH 4.3 V VI = VIH or VIL; IO = -100 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 2.2 V standard outputs: VI = VIH or VIL; VCC = 3.0 V; IO = -6 mA 6
HIGH-level output voltage VOH 3.5 V standard outputs: VI = VIH or VIL; VCC = 4.5 V; IO = -12 mA 6
LOW-level output voltage VOL 0.2 V VI = VIH or VIL; IO = 100 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.5 V standard outputs: VI = VIH or VIL; VCC = 3.0 V; IO = 6 mA 6
LOW-level output voltage VOL 0.65 V standard outputs: VI = VIH or VIL; VCC = 4.5 V; IO = 12 mA 6
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V 6
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 6
Additional supply current ΔICC 850 μA VI = VCC, 0.6 V; VCC = 2.7 V to 3.6 V 6
Maximum clock frequency fmax 12 MHz see Fig. 6; VCC = 2.0 V 8
Maximum clock frequency fmax 16 MHz see Fig. 6; VCC = 2.7 V 8
Maximum clock frequency fmax 20 MHz see Fig. 6; VCC = 3.0 V to 3.6 V 8
Maximum clock frequency fmax 30 MHz see Fig. 6; VCC = 4.5 V to 5.5 V 8
Propagation delay CE, CP to Q7, Q7 tpd 76 ns see Fig. 6 and Fig. 7; VCC = 2.0 V 7
Propagation delay CE, CP to Q7, Q7 tpd 54 ns see Fig. 6 and Fig. 7; VCC = 2.7 V 7
Propagation delay CE, CP to Q7, Q7 tpd 45 ns see Fig. 6 and Fig. 7; VCC = 3.0 V to 3.6 V 7
Propagation delay CE, CP to Q7, Q7 tpd 30 ns see Fig. 6 and Fig. 7; VCC = 4.5 V to 5.5 V 7
Propagation delay PL to Q7, Q7 tpd 70 ns see Fig. 7; VCC = 2.0 V 7
Propagation delay PL to Q7, Q7 tpd 49 ns see Fig. 7; VCC = 2.7 V 7
Propagation delay PL to Q7, Q7 tpd 41 ns see Fig. 7; VCC = 3.0 V to 3.6 V 7
Propagation delay PL to Q7, Q7 tpd 27 ns see Fig. 7; VCC = 4.5 V to 5.5 V 7
Propagation delay D7 to Q7, Q7 tpd 56 ns see Fig. 8; VCC = 2.0 V 7
Propagation delay D7 to Q7, Q7 tpd 40 ns see Fig. 8; VCC = 2.7 V 7
Propagation delay D7 to Q7, Q7 tpd 33 ns see Fig. 8; VCC = 3.0 V to 3.6 V 7
Propagation delay D7 to Q7, Q7 tpd 22 ns see Fig. 8; VCC = 4.5 V to 5.5 V 7
Set-up time DS to CP, CE tsu 26 ns see Fig. 9; VCC = 2.0 V 8
Set-up time DS to CP, CE tsu 19 ns see Fig. 9; VCC = 2.7 V 8
Set-up time DS to CP, CE tsu 15 ns see Fig. 9; VCC = 3.0 V to 3.6 V 8
Set-up time DS to CP, CE tsu 10 ns see Fig. 9; VCC = 4.5 V to 5.5 V 8
Hold time CE to CP, CP to CE th 5 ns see Fig. 9; VCC = 2.0 V 8

CAD (KiCad official)

  • Symbol: 74LV165PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74lv165pw-etched.step / 74lv165pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv165pw.step / 74lv165pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 539f61cb7d336063, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF