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74LV164PW

Public Made by Adom

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Nexperia Shift Registers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LV164PW

Nexperia · Shift Registers · TSSOP-14

74LV164PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DSA input Serial data input SA; either DSA or DSB can be used as an active HIGH enable for data entry through the other input.
2 DSB input Serial data input SB; either DSA or DSB can be used as an active HIGH enable for data entry through the other input.
3 Q0 output Parallel data output 0; forced LOW by a LOW on master reset MR.
4 Q1 output Parallel data output 1; forced LOW by a LOW on master reset MR.
5 Q2 output Parallel data output 2; forced LOW by a LOW on master reset MR.
6 Q3 output Parallel data output 3; forced LOW by a LOW on master reset MR.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 CP input Clock input, edge triggered on the LOW-to-HIGH transition; data is shifted on this transition.
9 MR input Asynchronous master reset input (active LOW); a LOW clears the register and forces all outputs LOW independently of other inputs.
10 Q4 output Parallel data output 4; forced LOW by a LOW on master reset MR.
11 Q5 output Parallel data output 5; forced LOW by a LOW on master reset MR.
12 Q6 output Parallel data output 6; forced LOW by a LOW on master reset MR.
13 Q7 output Parallel data output 7; forced LOW by a LOW on master reset MR.
14 VCC power_in Supply voltage; recommended operating range is 1.0 V to 5.5 V referenced to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -50 50 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage VCC 1 3.3 5.5 V 4
input voltage VI 0 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 25 125 °C 4
input transition rise and fall rate Δt/ΔV 500 ns/V VCC = 1.0 V to 2.0 V 4
input transition rise and fall rate Δt/ΔV 200 ns/V VCC = 2.0 V to 2.7 V 4
input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 2.7 V to 3.6 V 4
input transition rise and fall rate Δt/ΔV 50 ns/V VCC = 3.6 V to 5.5 V 4
HIGH-level input voltage VIH 0.9 V VCC = 1.2 V 5
HIGH-level input voltage VIH 1.4 V VCC = 2.0 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 0.3 V VCC = 1.2 V 5
LOW-level input voltage VIL 0.6 V VCC = 2.0 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
HIGH-level output voltage VOH 1.8 2 V IO = -100 μA; VCC = 2.0 V 5
HIGH-level output voltage VOH 2.5 2.7 V IO = -100 μA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2.8 3 V IO = -100 μA; VCC = 3.0 V 5
HIGH-level output voltage VOH 4.3 4.5 V IO = -100 μA; VCC = 4.5 V 5
HIGH-level output voltage VOH 2.2 2.82 V IO = -6 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 3.5 4.2 V IO = -12 mA; VCC = 4.5 V 5
LOW-level output voltage VOL 0 0.2 V IO = 100 μA; VCC = 2.0 V 5
LOW-level output voltage VOL 0.25 0.5 V IO = 6 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.35 0.65 V IO = 12 mA; VCC = 4.5 V 5
input leakage current II 1 μA VI = VCC or GND; VCC = 5.5 V 5
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 5
additional supply current per input ΔICC 850 μA per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V 5
propagation delay CP to Qn tpd 26 49 ns CP to Qn; see Fig. 4; VCC = 2.0 V 6
propagation delay CP to Qn tpd 19 36 ns CP to Qn; see Fig. 4; VCC = 2.7 V 6
propagation delay CP to Qn tpd 14 29 ns CP to Qn; see Fig. 4; VCC = 3.0 V to 3.6 V 6
propagation delay CP to Qn tpd 12 24 ns CP to Qn; see Fig. 4; VCC = 4.5 V to 5.5 V 6
recovery time trec 24 10 ns MR to CP; see Fig. 5; VCC = 2.0 V 6
recovery time trec 18 8 ns MR to CP; see Fig. 5; VCC = 2.7 V 6
recovery time trec 14 6 ns MR to CP; see Fig. 5; VCC = 3.0 V to 3.6 V 6
recovery time trec 10 5 ns MR to CP; see Fig. 5; VCC = 4.5 V to 5.5 V 6
set-up time tsu 26 5 ns Dn to CP; see Fig. 6; VCC = 2.0 V 6
set-up time tsu 19 4 ns Dn to CP; see Fig. 6; VCC = 2.7 V 6
set-up time tsu 15 3 ns Dn to CP; see Fig. 6; VCC = 3.0 V to 3.6 V 6
set-up time tsu 10 2 ns Dn to CP; see Fig. 6; VCC = 4.5 V to 5.5 V 6
hold time th 5 -3 ns Dn to CP; see Fig. 6; VCC = 2.0 V 7
hold time th 5 -2 ns Dn to CP; see Fig. 6; VCC = 2.7 V 7
hold time th 5 -1 ns Dn to CP; see Fig. 6; VCC = 4.5 V to 5.5 V 7
maximum frequency fmax 12 40 MHz see Fig. 4; VCC = 2.0 V 7
maximum frequency fmax 16 58 MHz see Fig. 4; VCC = 2.7 V 7
maximum frequency fmax 20 70 MHz see Fig. 4; VCC = 3.0 V to 3.6 V 7
maximum frequency fmax 30 100 MHz see Fig. 4; VCC = 4.5 V to 5.5 V 7

CAD (KiCad official)

  • Symbol: 74LV164PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lv164pw-etched.step / 74lv164pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv164pw.step / 74lv164pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 f09bf6848234d0cf, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF