# 74LV14BQ

**Nexperia** · Inverters · DHVQFN-14-EP(2.5x3)

74LV14BQ from Nexperia, in a DHVQFN-14-EP(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverting Schmitt-trigger buffer 1; input voltage must stay between 0 V and VCC (Table 5). |
| 2 | 1Y | output | Data output of inverting Schmitt-trigger buffer 1; output voltage must stay between 0 V and VCC and output current is limited to ±25 mA (Table 4). |
| 3 | 2A | input | Data input of inverting Schmitt-trigger buffer 2; input voltage must stay between 0 V and VCC (Table 5). |
| 4 | 2Y | output | Data output of inverting Schmitt-trigger buffer 2; output voltage must stay between 0 V and VCC and output current is limited to ±25 mA (Table 4). |
| 5 | 3A | input | Data input of inverting Schmitt-trigger buffer 3; input voltage must stay between 0 V and VCC (Table 5). |
| 6 | 3Y | output | Data output of inverting Schmitt-trigger buffer 3; output voltage must stay between 0 V and VCC and output current is limited to ±25 mA (Table 4). |
| 7 | GND | power_in | Ground (0 V) reference for all device voltages. |
| 8 | 4Y | output | Data output of inverting Schmitt-trigger buffer 4; output voltage must stay between 0 V and VCC and output current is limited to ±25 mA (Table 4). |
| 9 | 4A | input | Data input of inverting Schmitt-trigger buffer 4; input voltage must stay between 0 V and VCC (Table 5). |
| 10 | 5Y | output | Data output of inverting Schmitt-trigger buffer 5; output voltage must stay between 0 V and VCC and output current is limited to ±25 mA (Table 4). |
| 11 | 5A | input | Data input of inverting Schmitt-trigger buffer 5; input voltage must stay between 0 V and VCC (Table 5). |
| 12 | 6Y | output | Data output of inverting Schmitt-trigger buffer 6; output voltage must stay between 0 V and VCC and output current is limited to ±25 mA (Table 4). |
| 13 | 6A | input | Data input of inverting Schmitt-trigger buffer 6; input voltage must stay between 0 V and VCC (Table 5). |
| 14 | VCC | power_in | Supply voltage; recommended range is 1.0 V to 5.5 V (Table 5). |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-14-EP(2.5x3) |
| Category | Logic |
| Pins | 15 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage (absolute maximum) | VCC | -0.5 |  | 7 | V |  | 4 |
| input clamping current | IIK | -20 |  | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| output clamping current | IOK | -50 |  | 50 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| output current | IO | -25 |  | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 |
| supply current | ICC |  |  | 50 | mA |  | 4 |
| ground current | IGND | -50 |  |  | mA |  | 4 |
| storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| total power dissipation | Ptot |  |  | 500 | mW | Tamb = -40 °C to +125 °C | 4 |
| supply voltage (recommended) | VCC | 1 | 3.3 | 5.5 | V |  | 4 |
| input voltage | VI | 0 |  |  | V |  | 4 |
| output voltage | VO | 0 |  |  | V |  | 4 |
| ambient temperature | Tamb | -40 | 25 | 125 | °C |  | 4 |
| HIGH-level output voltage | VOH | 1.8 | 2 |  | V | VI = VT+ or VT-; IO = -100 μA; VCC = 2.0 V | 5 |
| HIGH-level output voltage | VOH | 2.5 | 2.7 |  | V | VI = VT+ or VT-; IO = -100 μA; VCC = 2.7 V | 5 |
| HIGH-level output voltage | VOH | 2.8 | 3 |  | V | VI = VT+ or VT-; IO = -100 μA; VCC = 3.0 V | 5 |
| HIGH-level output voltage | VOH | 4.3 | 4.5 |  | V | VI = VT+ or VT-; IO = -100 μA; VCC = 4.5 V | 5 |
| HIGH-level output voltage | VOH | 2.2 | 2.82 |  | V | VI = VT+ or VT-; IO = -6 mA; VCC = 3.0 V | 5 |
| HIGH-level output voltage | VOH | 3.5 | 4.2 |  | V | VI = VT+ or VT-; IO = -12 mA; VCC = 4.5 V | 5 |
| LOW-level output voltage | VOL |  | 0 | 0.2 | V | VI = VT+ or VT-; IO = 100 μA; VCC = 2.0 V | 5 |
| LOW-level output voltage | VOL |  | 0.25 | 0.5 | V | VI = VT+ or VT-; IO = 6 mA; VCC = 3.0 V | 5 |
| LOW-level output voltage | VOL |  | 0.35 | 0.65 | V | VI = VT+ or VT-; IO = 12 mA; VCC = 4.5 V | 5 |
| input leakage current | II |  |  | 1 | μA | VI = VCC or GND; VCC = 5.5 V | 5 |
| supply current | ICC |  |  | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 5 |
| additional supply current | ΔICC |  |  | 850 | μA | per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V | 5 |
| propagation delay nA to nY | tpd |  | 27 | 48 | ns | nA to nY; see Fig. 4; VCC = 2.0 V | 6 |
| propagation delay nA to nY | tpd |  | 20 | 35 | ns | nA to nY; see Fig. 4; VCC = 2.7 V | 6 |
| propagation delay nA to nY | tpd |  | 15 | 28 | ns | nA to nY; see Fig. 4; VCC = 3.0 V to 3.6 V | 6 |
| propagation delay nA to nY | tpd |  |  | 23 | ns | nA to nY; see Fig. 4; VCC = 4.5 V to 5.5 V | 6 |
| positive-going threshold voltage | VT+ | 0.8 | 1.1 | 1.4 | V | VCC = 2.0 V | 7 |
| positive-going threshold voltage | VT+ | 1 | 1.45 | 2 | V | VCC = 2.7 V | 7 |
| positive-going threshold voltage | VT+ | 1.2 | 1.6 | 2.2 | V | VCC = 3.0 V | 7 |
| positive-going threshold voltage | VT+ | 1.5 | 1.95 | 2.4 | V | VCC = 3.6 V | 7 |
| positive-going threshold voltage | VT+ | 1.7 | 2.5 | 3.15 | V | VCC = 4.5 V | 7 |
| positive-going threshold voltage | VT+ | 2.1 | 3 | 3.85 | V | VCC = 5.5 V | 7 |
| negative-going threshold voltage | VT- | 0.3 | 0.65 | 0.9 | V | VCC = 2.0 V | 7 |
| negative-going threshold voltage | VT- | 0.4 | 0.9 | 1.4 | V | VCC = 2.7 V | 7 |
| negative-going threshold voltage | VT- | 0.6 | 1.05 | 1.5 | V | VCC = 3.0 V | 7 |
| negative-going threshold voltage | VT- | 0.8 | 1.3 | 1.8 | V | VCC = 3.6 V | 7 |
| negative-going threshold voltage | VT- | 0.9 | 1.6 | 2 | V | VCC = 4.5 V | 7 |
| negative-going threshold voltage | VT- | 1.1 | 2 | 2.6 | V | VCC = 5.5 V | 7 |
| hysteresis voltage | VH | 0.2 | 0.55 | 0.8 | V | VCC = 2.0 V | 8 |
| hysteresis voltage | VH | 0.3 | 0.6 | 1.1 | V | VCC = 2.7 V | 8 |
| hysteresis voltage | VH | 0.4 | 0.65 | 1.2 | V | VCC = 3.0 V | 8 |
| hysteresis voltage | VH | 0.4 | 0.7 | 1.2 | V | VCC = 3.6 V | 8 |
| hysteresis voltage | VH | 0.4 | 0.8 | 1.4 | V | VCC = 4.5 V | 8 |
| hysteresis voltage | VH | 0.6 | 1 | 1.5 | V | VCC = 5.5 V | 8 |

## CAD (KiCad official)

- Symbol: `74LV14BQ`
- Footprint: `Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm`
- 3D model: DHVQFN-14-EP(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `74lv14bq-etched.step` / `74lv14bq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lv14bq.step` / `74lv14bq.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74LV14BQ.pdf) (15 pp, sha256 `91070d02ff13a940`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lv14bq-datasheet.pdf)