component

74LV132PW-Q100J

Public Made by Adom

by adom

Nexperia Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic ics74lv132pw-q100jfactory-2.0.0extractor-text

Verified 74LV132PW-Q100J

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 74LV132PW-Q100J · TSSOP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 15-page datasheet
  • ✓distributor: lcsc C547892, digikey 1727-74LV132PW-Q100JTR-ND, mouser 771-74LV132PWQ100J
  • ✓family: TSSOP-14_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rok4ui45/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.11)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 74lv132pw-q100j.kicad_sym✓ 74lv132pw-q100j.kicad_mod✓ 74lv132pw-q100j.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8h ago
viewers 74lv132pw-q100j: viewers · Ray 8h ago
74lv132pw-q100j-etched.glb Publish 0.1.0 · Ray 8h ago
74lv132pw-q100j-etched.step 74lv132pw-q100j: factory component page (tier=mfr) · Ray 8h ago
74lv132pw-q100j-hero.glb 74lv132pw-q100j: hero GLB from the etched model (keeps the MPN mark) · Ray 8h ago
74lv132pw-q100j-hero.overlay.json Publish 0.1.0 · Ray 8h ago
74lv132pw-q100j.glb Publish 0.1.0 · Ray 8h ago
74lv132pw-q100j.kicad_mod Publish 0.1.0 · Ray 8h ago
74lv132pw-q100j.kicad_sym Publish 0.1.0 · Ray 8h ago
74lv132pw-q100j.lbr Publish 0.1.0 · Ray 8h ago
74lv132pw-q100j.step Publish 0.1.0 · Ray 8h ago
package.json Publish 0.1.0 · Ray 8h ago
page.json Set visibility: public · Ray 8h ago
README.md Publish 0.1.0 · Ray 8h ago
verification.json Verified: Published by the parts factory: tier mfr, 14 pins · Ray 8h ago

74LV132PW-Q100J

Nexperia · Gates · TSSOP-14

74LV132PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of NAND gate 1; input voltage range is 0 V to VCC (Table 5).
2 1B input Data input 1B of NAND gate 1; input voltage range is 0 V to VCC (Table 5).
3 1Y output Data output 1Y of NAND gate 1; output voltage range is 0 V to VCC (Table 5).
4 2A input Data input 2A of NAND gate 2; input voltage range is 0 V to VCC (Table 5).
5 2B input Data input 2B of NAND gate 2; input voltage range is 0 V to VCC (Table 5).
6 2Y output Data output 2Y of NAND gate 2; output voltage range is 0 V to VCC (Table 5).
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 3Y output Data output 3Y of NAND gate 3; output voltage range is 0 V to VCC (Table 5).
9 3A input Data input 3A of NAND gate 3; input voltage range is 0 V to VCC (Table 5).
10 3B input Data input 3B of NAND gate 3; input voltage range is 0 V to VCC (Table 5).
11 4Y output Data output 4Y of NAND gate 4; output voltage range is 0 V to VCC (Table 5).
12 4A input Data input 4A of NAND gate 4; input voltage range is 0 V to VCC (Table 5).
13 4B input Data input 4B of NAND gate 4; input voltage range is 0 V to VCC (Table 5).
14 VCC power_in Supply voltage; recommended operating range is 1.0 V to 5.5 V (Table 5), with absolute maximum of 7.0 V (Table 4).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V 4
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamping current IOK -50 50 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 4
Supply current ICC 50 mA 4
Ground current IGND -50 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
Supply voltage VCC 1 3.3 5.5 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Ambient temperature Tamb -40 25 125 °C 4
HIGH-level output voltage VOH 1.8 2 V VI = VT+ or VT-; IO = -100 μA; VCC = 2.0 V 5
HIGH-level output voltage VOH 2.5 2.7 V VI = VT+ or VT-; IO = -100 μA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2.8 3 V VI = VT+ or VT-; IO = -100 μA; VCC = 3.0 V 5
HIGH-level output voltage VOH 4.3 4.5 V VI = VT+ or VT-; IO = -100 μA; VCC = 4.5 V 5
HIGH-level output voltage VOH 2.2 2.82 V VI = VT+ or VT-; IO = -6 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 3.5 4.2 V VI = VT+ or VT-; IO = -12 mA; VCC = 4.5 V 5
LOW-level output voltage VOL 0 0.2 V VI = VT+ or VT-; IO = 100 μA; VCC = 2.0 V 5
LOW-level output voltage VOL 0.25 0.5 V VI = VT+ or VT-; IO = 6 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.35 0.65 V VI = VT+ or VT-; IO = 12 mA; VCC = 4.5 V 5
Input leakage current II 1 μA VI = VCC or GND; VCC = 5.5 V 5
Supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 5
Additional supply current ΔICC 850 μA per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V 5
Propagation delay nA, nB to nY tpd 18 43 ns VCC = 2.0 V 6
Propagation delay nA, nB to nY tpd 15 30 ns VCC = 2.7 V 6
Propagation delay nA, nB to nY tpd 12 25 ns VCC = 3.0 V to 3.6 V 6
Propagation delay nA, nB to nY tpd 9 17 ns VCC = 4.5 V to 5.5 V 6
Positive-going threshold voltage VT+ 0.8 1.1 1.4 V VCC = 2.0 V 8
Positive-going threshold voltage VT+ 1 1.45 2 V VCC = 2.7 V 8
Positive-going threshold voltage VT+ 1.2 1.6 2.2 V VCC = 3.0 V 8
Positive-going threshold voltage VT+ 1.5 1.95 2.4 V VCC = 3.6 V 8
Positive-going threshold voltage VT+ 1.7 2.5 3.2 V VCC = 4.5 V 8
Positive-going threshold voltage VT+ 2.1 3 3.9 V VCC = 5.5 V 8
Negative-going threshold voltage VT- 0.3 0.65 0.9 V VCC = 2.0 V 8
Negative-going threshold voltage VT- 0.4 0.9 1.4 V VCC = 2.7 V 8
Negative-going threshold voltage VT- 0.6 1.05 1.5 V VCC = 3.0 V 8
Negative-going threshold voltage VT- 0.8 1.3 1.8 V VCC = 3.6 V 8
Negative-going threshold voltage VT- 0.9 1.6 2 V VCC = 4.5 V 8
Negative-going threshold voltage VT- 1.2 2 2.6 V VCC = 5.5 V 8
Hysteresis voltage (VT+ - VT-) VH 0.2 0.55 0.8 V VCC = 2.0 V 8
Hysteresis voltage (VT+ - VT-) VH 0.3 0.6 1.1 V VCC = 2.7 V 8
Hysteresis voltage (VT+ - VT-) VH 0.4 0.65 1.2 V VCC = 3.0 V 8
Hysteresis voltage (VT+ - VT-) VH 0.4 0.7 1.2 V VCC = 3.6 V 8
Hysteresis voltage (VT+ - VT-) VH 0.4 0.8 1.4 V VCC = 4.5 V 8
Hysteresis voltage (VT+ - VT-) VH 0.6 1 1.5 V VCC = 5.5 V 8

CAD (KiCad official)

  • Symbol: 74LV132PW-Q100J
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lv132pw-q100j-etched.step / 74lv132pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv132pw-q100j.step / 74lv132pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 2e6629a5325954a9, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF