# 74LV08PW

**Nexperia** · Logic Gates · TSSOP-14

74LV08PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 2 | 1B | input | Data input 1B of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 3 | 1Y | output | Data output 1Y of the AND gate; output current limited to ±25 mA over VO = -0.5 V to (VCC + 0.5 V). |
| 4 | 2A | input | Data input 2A of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 5 | 2B | input | Data input 2B of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 6 | 2Y | output | Data output 2Y of the AND gate; output current limited to ±25 mA over VO = -0.5 V to (VCC + 0.5 V). |
| 7 | GND | power_in | Ground (0 V) reference for all voltages in the datasheet; ground current limited to -50 mA. |
| 8 | 3Y | output | Data output 3Y of the AND gate; output current limited to ±25 mA over VO = -0.5 V to (VCC + 0.5 V). |
| 9 | 3A | input | Data input 3A of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 10 | 3B | input | Data input 3B of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 11 | 4Y | output | Data output 4Y of the AND gate; output current limited to ±25 mA over VO = -0.5 V to (VCC + 0.5 V). |
| 12 | 4A | input | Data input 4A of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 13 | 4B | input | Data input 4B of the 2-input AND gate; inputs include clamp diodes so current-limiting resistors can interface inputs to voltages above VCC, with input clamping current limited to ±20 mA. |
| 14 | VCC | power_in | Supply voltage, recommended range 1.0 V to 5.5 V; absolute maximum supply voltage is 7.0 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 |  | 7 | V |  | 3 |
| input clamping current | IIK | -20 |  | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 3 |
| output clamping current | IOK | -50 |  | 50 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 |
| output current | IO | -25 |  | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 3 |
| supply current | ICC |  |  | 50 | mA |  | 3 |
| ground current | IGND | -50 |  |  | mA |  | 3 |
| storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| total power dissipation | Ptot |  |  | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| supply voltage | VCC | 1 | 3.3 | 5.5 | V |  | 3 |
| ambient temperature | Tamb | -40 | 25 | 125 | °C |  | 3 |
| input transition rise and fall rate | Δt/ΔV |  |  | 500 | ns/V | VCC = 1.0 V to 2.0 V | 3 |
| input transition rise and fall rate | Δt/ΔV |  |  | 200 | ns/V | VCC = 2.0 V to 2.7 V | 3 |
| input transition rise and fall rate | Δt/ΔV |  |  | 100 | ns/V | VCC = 2.7 V to 3.6 V | 3 |
| input transition rise and fall rate | Δt/ΔV |  |  | 50 | ns/V | VCC = 3.6 V to 5.5 V | 3 |
| HIGH-level input voltage | VIH | 0.9 |  |  | V | VCC = 1.2 V | 4 |
| HIGH-level input voltage | VIH | 1.4 |  |  | V | VCC = 2.0 V | 4 |
| HIGH-level input voltage | VIH | 2 |  |  | V | VCC = 2.7 V to 3.6 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.3 | V | VCC = 1.2 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.6 | V | VCC = 2.0 V | 4 |
| LOW-level input voltage | VIL |  |  | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 |
| HIGH-level output voltage | VOH | 1.8 | 2 |  | V | IO = -100 μA; VCC = 2.0 V | 4 |
| HIGH-level output voltage | VOH | 2.5 | 2.7 |  | V | IO = -100 μA; VCC = 2.7 V | 4 |
| HIGH-level output voltage | VOH | 2.8 | 3 |  | V | IO = -100 μA; VCC = 3.0 V | 4 |
| HIGH-level output voltage | VOH | 4.3 | 4.5 |  | V | IO = -100 μA; VCC = 4.5 V | 4 |
| HIGH-level output voltage | VOH | 2.2 | 2.82 |  | V | IO = -6 mA; VCC = 3.0 V | 4 |
| HIGH-level output voltage | VOH | 3.5 | 4.2 |  | V | IO = -12 mA; VCC = 4.5 V | 4 |
| LOW-level output voltage | VOL |  | 0 | 0.2 | V | IO = 100 μA; VCC = 2.0 V | 4 |
| LOW-level output voltage | VOL |  | 0.25 | 0.5 | V | IO = 6 mA; VCC = 3.0 V | 4 |
| LOW-level output voltage | VOL |  | 0.35 | 0.65 | V | IO = 12 mA; VCC = 4.5 V | 4 |
| input leakage current | II |  |  | 1 | μA | VI = VCC or GND; VCC = 5.5 V | 4 |
| supply current | ICC |  |  | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 |
| additional supply current | ΔICC |  |  | 850 | μA | per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V | 4 |
| propagation delay | tpd |  | 15 | 33 | ns | nA, nB to nY; VCC = 2.0 V | 5 |
| propagation delay | tpd |  | 11 | 21 | ns | nA, nB to nY; VCC = 2.7 V | 5 |
| propagation delay | tpd |  | 9 | 19 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V | 5 |
| propagation delay | tpd |  |  | 14 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V | 5 |

## CAD (KiCad official)

- Symbol: `74LV08PW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74lv08pw-etched.step` / `74lv08pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lv08pw.step` / `74lv08pw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74LV08PW.pdf) (11 pp, sha256 `bf536eb399a90a0d`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lv08pw-datasheet.pdf)