component
74LV08APWJ
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74LV08APWJ
Nexperia · Logic Gates · TSSOP-14
74LV08APWJ from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1 (1Y = 1A AND 1B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 2 | 1B | input | Data input of gate 1 (1Y = 1A AND 1B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 3 | 1Y | output | Data output of gate 1; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 4 | 2A | input | Data input of gate 2 (2Y = 2A AND 2B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 5 | 2B | input | Data input of gate 2 (2Y = 2A AND 2B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 6 | 2Y | output | Data output of gate 2; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output of gate 3; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 9 | 3A | input | Data input of gate 3 (3Y = 3A AND 3B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 10 | 3B | input | Data input of gate 3 (3Y = 3A AND 3B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 11 | 4Y | output | Data output of gate 4; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 12 | 4A | input | Data input of gate 4 (4Y = 4A AND 4B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 13 | 4B | input | Data input of gate 4 (4Y = 4A AND 4B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 14 | VCC | power_in | Supply voltage; recommended operating range is 2.0 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| input voltage | VI | -0.5 | 7 | V | 3 | ||
| output voltage | VO | -0.5 | V | output HIGH or LOW state | 3 | ||
| output voltage | VO | -0.5 | 7 | V | output power-down | 3 | |
| input clamping current | IIK | -20 | mA | VI < 0 V | 3 | ||
| output clamping current | IOK | -50 | mA | VO < 0 V | 3 | ||
| output current | IO | -35 | 35 | mA | VO = 0 V to VCC | 3 | |
| supply current | ICC | 70 | mA | 3 | |||
| ground current | IGND | -70 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| supply voltage | VCC | 2 | 5 | 5.5 | V | 4 | |
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage | VO | 0 | V | output HIGH or LOW state | 4 | ||
| output voltage | VO | 0 | 5.5 | V | output power-down | 4 | |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| input transition rise and fall rate | Δt/ΔV | 200 | ns/V | VCC = 2.3 V to 2.7 V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC = 2 V | 4 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC = 2 V | 4 | ||
| HIGH-level output voltage | VOH | 2 | V | VI = VIH or VIL; VCC = 2.3 V; IO = -2 mA | 4 | ||
| HIGH-level output voltage | VOH | 2.48 | V | VI = VIH or VIL; VCC = 3.0 V; IO = -6 mA | 4 | ||
| HIGH-level output voltage | VOH | 3.8 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -12 mA | 4 | ||
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; VCC = 2.0 V to 5.5 V; IO = 50 µA | 4 | ||
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; VCC = 2.3 V; IO = 2 mA | 4 | ||
| LOW-level output voltage | VOL | 0.44 | V | VI = VIH or VIL; VCC = 3.0 V; IO = 6 mA | 4 | ||
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 12 mA | 4 | ||
| power-off leakage current | IOFF | 5 | µA | VI or VO = GND to 5.5 V; VCC = 0 V | 4 | ||
| input leakage current | II | -1 | 1 | µA | VI = VCC or GND; VCC = 0 V to 5.5 V | 4 | |
| supply current | ICC | 20 | µA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 | ||
| propagation delay | tpd | 1 | 5.6 | 17 | ns | nA, nB to nY; VCC = 2.3 V to 2.7 V; CL = 15 pF | 5 |
| propagation delay | tpd | 1 | 7.8 | 21 | ns | nA, nB to nY; VCC = 2.3 V to 2.7 V; CL = 50 pF | 5 |
| propagation delay | tpd | 1 | 4.3 | 11.5 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF | 5 |
| propagation delay | tpd | 1 | 6 | 15 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF | 5 |
| propagation delay | tpd | 1 | 3.3 | 8 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF | 5 |
| propagation delay | tpd | 1 | 4.8 | 10 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF | 5 |
| input capacitance | CI | 2 | 6 | pF | VI = VCC or GND; VCC = 3.3 V | 5 | |
| LOW-level output voltage (peak) | VOL(p) | 0.2 | 0.8 | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 | |
| LOW-level output voltage (valley) | VOL(v) | -0.8 | -0.1 | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 | |
| AC HIGH-level input voltage | VIH(AC) | 2.31 | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 | ||
| AC LOW-level input voltage | VIL(AC) | 0.99 | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 |
CAD (KiCad official)
- Symbol:
74LV08APWJ - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74lv08apwj-etched.step/74lv08apwj-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lv08apwj.step/74lv08apwj.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (10 pp, sha256
ae09d24e85819ffb, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74LV08APWJ
**Nexperia** · Logic Gates · TSSOP-14
74LV08APWJ from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1 (1Y = 1A AND 1B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 2 | 1B | input | Data input of gate 1 (1Y = 1A AND 1B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 3 | 1Y | output | Data output of gate 1; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 4 | 2A | input | Data input of gate 2 (2Y = 2A AND 2B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 5 | 2B | input | Data input of gate 2 (2Y = 2A AND 2B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 6 | 2Y | output | Data output of gate 2; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output of gate 3; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 9 | 3A | input | Data input of gate 3 (3Y = 3A AND 3B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 10 | 3B | input | Data input of gate 3 (3Y = 3A AND 3B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 11 | 4Y | output | Data output of gate 4; IOFF circuitry disables this output during power-down, and output current is limited to ±35 mA. |
| 12 | 4A | input | Data input of gate 4 (4Y = 4A AND 4B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 13 | 4B | input | Data input of gate 4 (4Y = 4A AND 4B); overvoltage tolerant, with Schmitt-trigger action and a recommended input voltage range of 0 V to 5.5 V. |
| 14 | VCC | power_in | Supply voltage; recommended operating range is 2.0 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| input voltage | VI | -0.5 | | 7 | V | | 3 |
| output voltage | VO | -0.5 | | | V | output HIGH or LOW state | 3 |
| output voltage | VO | -0.5 | | 7 | V | output power-down | 3 |
| input clamping current | IIK | -20 | | | mA | VI < 0 V | 3 |
| output clamping current | IOK | -50 | | | mA | VO < 0 V | 3 |
| output current | IO | -35 | | 35 | mA | VO = 0 V to VCC | 3 |
| supply current | ICC | | | 70 | mA | | 3 |
| ground current | IGND | -70 | | | mA | | 3 |
| storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
| supply voltage | VCC | 2 | 5 | 5.5 | V | | 4 |
| input voltage | VI | 0 | | 5.5 | V | | 4 |
| output voltage | VO | 0 | | | V | output HIGH or LOW state | 4 |
| output voltage | VO | 0 | | 5.5 | V | output power-down | 4 |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 200 | ns/V | VCC = 2.3 V to 2.7 V | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 |
| HIGH-level input voltage | VIH | 1.5 | | | V | VCC = 2 V | 4 |
| LOW-level input voltage | VIL | | | 0.5 | V | VCC = 2 V | 4 |
| HIGH-level output voltage | VOH | 2 | | | V | VI = VIH or VIL; VCC = 2.3 V; IO = -2 mA | 4 |
| HIGH-level output voltage | VOH | 2.48 | | | V | VI = VIH or VIL; VCC = 3.0 V; IO = -6 mA | 4 |
| HIGH-level output voltage | VOH | 3.8 | | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -12 mA | 4 |
| LOW-level output voltage | VOL | | | 0.1 | V | VI = VIH or VIL; VCC = 2.0 V to 5.5 V; IO = 50 µA | 4 |
| LOW-level output voltage | VOL | | | 0.4 | V | VI = VIH or VIL; VCC = 2.3 V; IO = 2 mA | 4 |
| LOW-level output voltage | VOL | | | 0.44 | V | VI = VIH or VIL; VCC = 3.0 V; IO = 6 mA | 4 |
| LOW-level output voltage | VOL | | | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 12 mA | 4 |
| power-off leakage current | IOFF | | | 5 | µA | VI or VO = GND to 5.5 V; VCC = 0 V | 4 |
| input leakage current | II | -1 | | 1 | µA | VI = VCC or GND; VCC = 0 V to 5.5 V | 4 |
| supply current | ICC | | | 20 | µA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 4 |
| propagation delay | tpd | 1 | 5.6 | 17 | ns | nA, nB to nY; VCC = 2.3 V to 2.7 V; CL = 15 pF | 5 |
| propagation delay | tpd | 1 | 7.8 | 21 | ns | nA, nB to nY; VCC = 2.3 V to 2.7 V; CL = 50 pF | 5 |
| propagation delay | tpd | 1 | 4.3 | 11.5 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 15 pF | 5 |
| propagation delay | tpd | 1 | 6 | 15 | ns | nA, nB to nY; VCC = 3.0 V to 3.6 V; CL = 50 pF | 5 |
| propagation delay | tpd | 1 | 3.3 | 8 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 15 pF | 5 |
| propagation delay | tpd | 1 | 4.8 | 10 | ns | nA, nB to nY; VCC = 4.5 V to 5.5 V; CL = 50 pF | 5 |
| input capacitance | CI | | 2 | 6 | pF | VI = VCC or GND; VCC = 3.3 V | 5 |
| LOW-level output voltage (peak) | VOL(p) | | 0.2 | 0.8 | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 |
| LOW-level output voltage (valley) | VOL(v) | -0.8 | -0.1 | | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 |
| AC HIGH-level input voltage | VIH(AC) | 2.31 | | | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 |
| AC LOW-level input voltage | VIL(AC) | | | 0.99 | V | Tamb = 25 °C; VCC = 3.3 V; CL = 50 pF | 5 |
## CAD (KiCad official)
- Symbol: `74LV08APWJ`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74lv08apwj-etched.step` / `74lv08apwj-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lv08apwj.step` / `74lv08apwj.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908358711984129) (10 pp, sha256 `ae09d24e85819ffb`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74lv08apwj-datasheet.pdf)