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74LV04PW

Public Made by Adom

by adom

Nexperia Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LV04PW

Nexperia · Inverters · TSSOP-14

74LV04PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input of gate 1.
2 1Y output Data output of gate 1 (inverted 1A).
3 2A input Data input of gate 2.
4 2Y output Data output of gate 2 (inverted 2A).
5 3A input Data input of gate 3.
6 3Y output Data output of gate 3 (inverted 3A).
7 GND power_in Ground (0 V).
8 4Y output Data output of gate 4 (inverted 4A).
9 4A input Data input of gate 4.
10 5Y output Data output of gate 5 (inverted 5A).
11 5A input Data input of gate 5.
12 6Y output Data output of gate 6 (inverted 6A).
13 6A input Data input of gate 6.
14 VCC power_in Supply voltage, 1.0 V to 5.5 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 3
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 3
Output clamping current IOK -50 50 mA VO < -0.5 V or VO > VCC + 0.5 V 3
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 3
Supply current ICC 50 mA 3
Ground current IGND -50 mA 3
Storage temperature Tstg -65 150 °C 3
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
Supply voltage VCC 1 3.3 5.5 V 3
Input voltage VI 0 V max is VCC 3
Output voltage VO 0 V max is VCC 3
Ambient temperature Tamb -40 25 125 °C 3
Input transition rise and fall rate Δt/ΔV 500 ns/V VCC = 1.0 V to 2.0 V 3
Input transition rise and fall rate Δt/ΔV 200 ns/V VCC = 2.0 V to 2.7 V 3
Input transition rise and fall rate Δt/ΔV 100 ns/V VCC = 2.7 V to 3.6 V 3
Input transition rise and fall rate Δt/ΔV 50 ns/V VCC = 3.6 V to 5.5 V 3
Ptot derating (TSSOP14) Ptot 7.3 mW/K derates linearly above 81 °C, SOT402-1 3
HIGH-level input voltage VIH 0.9 V VCC = 1.2 V; -40 °C to +85 °C 4
HIGH-level input voltage VIH 1.4 V VCC = 2.0 V; -40 °C to +85 °C 4
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V; -40 °C to +85 °C 4
HIGH-level input voltage VIH 0.7 V VCC = 4.5 V to 5.5 V; min is 0.7VCC; -40 °C to +85 °C 4
LOW-level input voltage VIL 0.3 V VCC = 1.2 V; -40 °C to +85 °C 4
LOW-level input voltage VIL 0.6 V VCC = 2.0 V; -40 °C to +85 °C 4
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 1.2 V VI = VIH or VIL; IO = -100 µA; VCC = 1.2 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 1.8 2 V VI = VIH or VIL; IO = -100 µA; VCC = 2.0 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 2.5 2.7 V VI = VIH or VIL; IO = -100 µA; VCC = 2.7 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 2.8 3 V VI = VIH or VIL; IO = -100 µA; VCC = 3.0 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 4.3 4.5 V VI = VIH or VIL; IO = -100 µA; VCC = 4.5 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 2.4 2.82 V VI = VIH or VIL; IO = -6 mA; VCC = 3.0 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 3.6 4.2 V VI = VIH or VIL; IO = -12 mA; VCC = 4.5 V; -40 °C to +85 °C 4
LOW-level output voltage VOL 0 V VI = VIH or VIL; IO = 100 µA; VCC = 1.2 V; -40 °C to +85 °C 4
LOW-level output voltage VOL 0 0.2 V VI = VIH or VIL; IO = 100 µA; VCC = 2.0 V; -40 °C to +85 °C 4
LOW-level output voltage VOL 0.25 0.4 V VI = VIH or VIL; IO = 6 mA; VCC = 3.0 V; -40 °C to +85 °C 4
LOW-level output voltage VOL 0.35 0.55 V VI = VIH or VIL; IO = 12 mA; VCC = 4.5 V; -40 °C to +85 °C 4
Input leakage current II 1 µA VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C 4
Supply current ICC 20 µA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C 4
Additional supply current per input ΔICC 500 µA VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V; -40 °C to +85 °C 4
Input capacitance CI 3.5 pF 4
HIGH-level output voltage VOH 2.2 V VI = VIH or VIL; IO = -6 mA; VCC = 3.0 V; -40 °C to +125 °C 4
HIGH-level output voltage VOH 3.5 V VI = VIH or VIL; IO = -12 mA; VCC = 4.5 V; -40 °C to +125 °C 4
LOW-level output voltage VOL 0.5 V VI = VIH or VIL; IO = 6 mA; VCC = 3.0 V; -40 °C to +125 °C 4
LOW-level output voltage VOL 0.65 V VI = VIH or VIL; IO = 12 mA; VCC = 4.5 V; -40 °C to +125 °C 4
Supply current ICC 40 µA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 4
Additional supply current per input ΔICC 850 µA VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 4
Propagation delay nA to nY tpd 14 20 ns VCC = 2.0 V; -40 °C to +85 °C 5
Propagation delay nA to nY tpd 10 15 ns VCC = 2.7 V; -40 °C to +85 °C 5
Propagation delay nA to nY tpd 6 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; -40 °C to +85 °C 5
Propagation delay nA to nY tpd 8 12 ns VCC = 3.0 V to 3.6 V; -40 °C to +85 °C 5
Propagation delay nA to nY tpd 9 ns VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 5
Propagation delay nA to nY tpd 25 ns VCC = 2.0 V; -40 °C to +125 °C 5
Propagation delay nA to nY tpd 19 ns VCC = 2.7 V; -40 °C to +125 °C 5
Propagation delay nA to nY tpd 15 ns VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 5
Propagation delay nA to nY tpd 11 ns VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 5
Power dissipation capacitance CPD 21 pF CL = 50 pF; fi = 1 MHz; VI = GND to VCC 5

CAD (KiCad official)

  • Symbol: 74LV04PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lv04pw-etched.step / 74lv04pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lv04pw.step / 74lv04pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 576e649169cea5bc, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF