component
74LCX74MTCX
Public Made by Adomby adom
onsemi Logic ICs, TSSOP-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
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74LCX74MTCX
onsemi · Logic ICs · TSSOP-14
74LCX74MTCX from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CD1 | input | Active-low direct clear input of flip-flop 1; a LOW level sets Q1 LOW independent of the clock. |
| 2 | D1 | input | Data input of flip-flop 1, transferred to Q1 on the rising edge of CP1 (5V tolerant, VI max 5.5V). |
| 3 | CP1 | input | Clock pulse input of flip-flop 1, positive edge-triggered. |
| 4 | SD1 | input | Active-low direct set input of flip-flop 1; a LOW level sets Q1 HIGH independent of the clock. |
| 5 | Q1 | output | True output of flip-flop 1 with ±24mA drive at VCC = 3.0V-3.6V. |
| 6 | Q1_N | output | Complementary output of flip-flop 1 with ±24mA drive at VCC = 3.0V-3.6V. |
| 7 | GND | power_in | Ground pin (0V reference). |
| 8 | Q2_N | output | Complementary output of flip-flop 2 with ±24mA drive at VCC = 3.0V-3.6V. |
| 9 | Q2 | output | True output of flip-flop 2 with ±24mA drive at VCC = 3.0V-3.6V. |
| 10 | SD2 | input | Active-low direct set input of flip-flop 2; a LOW level sets Q2 HIGH independent of the clock. |
| 11 | CP2 | input | Clock pulse input of flip-flop 2, positive edge-triggered. |
| 12 | D2 | input | Data input of flip-flop 2, transferred to Q2 on the rising edge of CP2 (5V tolerant, VI max 5.5V). |
| 13 | CD2 | input | Active-low direct clear input of flip-flop 2; a LOW level sets Q2 LOW independent of the clock. |
| 14 | VCC | power_in | Supply voltage, 2.0V to 3.6V operating (2.3V-3.6V specified), absolute maximum -0.5V to +7.0V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
74LCX74MTCX - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74lcx74mtcx-etched.step/74lcx74mtcx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lcx74mtcx.step/74lcx74mtcx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
36c978ca2cfaf13f, retrieved 2026-10-21, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74LCX74MTCX
**onsemi** · Logic ICs · TSSOP-14
74LCX74MTCX from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CD1 | input | Active-low direct clear input of flip-flop 1; a LOW level sets Q1 LOW independent of the clock. |
| 2 | D1 | input | Data input of flip-flop 1, transferred to Q1 on the rising edge of CP1 (5V tolerant, VI max 5.5V). |
| 3 | CP1 | input | Clock pulse input of flip-flop 1, positive edge-triggered. |
| 4 | SD1 | input | Active-low direct set input of flip-flop 1; a LOW level sets Q1 HIGH independent of the clock. |
| 5 | Q1 | output | True output of flip-flop 1 with ±24mA drive at VCC = 3.0V-3.6V. |
| 6 | Q1_N | output | Complementary output of flip-flop 1 with ±24mA drive at VCC = 3.0V-3.6V. |
| 7 | GND | power_in | Ground pin (0V reference). |
| 8 | Q2_N | output | Complementary output of flip-flop 2 with ±24mA drive at VCC = 3.0V-3.6V. |
| 9 | Q2 | output | True output of flip-flop 2 with ±24mA drive at VCC = 3.0V-3.6V. |
| 10 | SD2 | input | Active-low direct set input of flip-flop 2; a LOW level sets Q2 HIGH independent of the clock. |
| 11 | CP2 | input | Clock pulse input of flip-flop 2, positive edge-triggered. |
| 12 | D2 | input | Data input of flip-flop 2, transferred to Q2 on the rising edge of CP2 (5V tolerant, VI max 5.5V). |
| 13 | CD2 | input | Active-low direct clear input of flip-flop 2; a LOW level sets Q2 LOW independent of the clock. |
| 14 | VCC | power_in | Supply voltage, 2.0V to 3.6V operating (2.3V-3.6V specified), absolute maximum -0.5V to +7.0V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `74LCX74MTCX`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74lcx74mtcx-etched.step` / `74lcx74mtcx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lcx74mtcx.step` / `74lcx74mtcx.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/74lcx74mtcx-d.pdf) (13 pp, sha256 `36c978ca2cfaf13f`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74lcx74mtcx-datasheet.pdf)