main
History Download
Ray Publish 0.1.0 2d191f5 9h ago

74LCX74MTC

onsemi · Flip Flops · TSSOP-14

74LCX74MTC from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CD1 input Active-low direct clear input of flip-flop 1; a LOW sets Q1 LOW independent of the clock, and the input is 5V tolerant (VI up to 5.5V).
2 D1 input Data input of flip-flop 1, transferred to Q1 on the LOW-to-HIGH clock transition; 5V tolerant.
3 CP1 input Clock pulse input of flip-flop 1, positive edge triggered; 5V tolerant.
4 SD1 input Active-low direct set input of flip-flop 1; a LOW sets Q1 HIGH independent of the clock, and the input is 5V tolerant.
5 Q1 output True output of flip-flop 1, with ±24mA drive at VCC = 3.0V to 3.6V.
6 Q1̅ output Complementary output of flip-flop 1, with ±24mA drive at VCC = 3.0V to 3.6V.
7 GND power_in Ground pin (0V reference).
8 Q2̅ output Complementary output of flip-flop 2, with ±24mA drive at VCC = 3.0V to 3.6V.
9 Q2 output True output of flip-flop 2, with ±24mA drive at VCC = 3.0V to 3.6V.
10 SD2 input Active-low direct set input of flip-flop 2; a LOW sets Q2 HIGH independent of the clock, and the input is 5V tolerant.
11 CP2 input Clock pulse input of flip-flop 2, positive edge triggered; 5V tolerant.
12 D2 input Data input of flip-flop 2, transferred to Q2 on the LOW-to-HIGH clock transition; 5V tolerant.
13 CD2 input Active-low direct clear input of flip-flop 2; a LOW sets Q2 LOW independent of the clock, and the input is 5V tolerant.
14 VCC power_in Supply voltage pin, 2.0V to 3.6V operating (2.3V to 3.6V specified), with absolute maximum of 7.0V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
HIGH Level Input Voltage VIH 1.7 V VCC = 2.3-2.7 V, TA = -40 to +85 °C 5
HIGH Level Input Voltage VIH 2 V VCC = 2.7-3.6 V, TA = -40 to +85 °C 5
LOW Level Input Voltage VIL 0.7 V VCC = 2.3-2.7 V, TA = -40 to +85 °C 5
LOW Level Input Voltage VIL 0.8 V VCC = 2.7-3.6 V, TA = -40 to +85 °C 5
HIGH Level Output Voltage VOH 1.8 V VCC = 2.3 V, IOH = -8 mA 5
HIGH Level Output Voltage VOH 2.2 V VCC = 2.7 V, IOH = -12 mA 5
HIGH Level Output Voltage VOH 2.4 V VCC = 3.0 V, IOH = -18 mA 5
LOW Level Output Voltage VOL 0.2 V VCC = 2.3-3.6 V, IOL = 100 µA 5
LOW Level Output Voltage VOL 0.6 V VCC = 2.3 V, IOL = 8 mA 5
LOW Level Output Voltage VOL 0.4 V VCC = 2.7 V, IOL = 12 mA 5
LOW Level Output Voltage VOL 0.55 V IOL = 24 mA 5
Input Leakage Current II -5 5 µA VCC = 2.3-3.6 V, 0 ≤ VI ≤ 5.5 V 5
Quiescent Supply Current ICC 10 µA VCC = 2.3-3.6 V, VI = VCC or GND 5
Quiescent Supply Current ICC -10 10 µA VCC = 2.3-3.6 V, 3.6 V ≤ VI ≤ 5.5 V 5
Increase in ICC per Input ΔICC 500 µA VCC = 2.3-3.6 V, VIH = VCC, 0.6 V 5
Maximum Clock Frequency fMAX 150 MHz VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Propagation Delay, CPn to Qn or Qn tPHL, tPLH 1.5 7 ns VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Propagation Delay, CPn to Qn or Qn tPHL, tPLH 1.5 8 ns VCC = 2.7 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Propagation Delay, CPn to Qn or Qn tPHL, tPLH 1.5 8.4 ns VCC = 2.5 V ±0.2 V, CL = 30 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Propagation Delay, CDn or SDn to Qn or Qn tPHL, tPLH 1.5 7 ns VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Propagation Delay, CDn or SDn to Qn or Qn tPHL, tPLH 1.5 8 ns VCC = 2.7 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Propagation Delay, CDn or SDn to Qn or Qn tPHL, tPLH 1.5 8.4 ns VCC = 2.5 V ±0.2 V, CL = 30 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Setup Time tS 2.5 ns VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Setup Time tS 4 ns VCC = 2.5 V ±0.2 V, CL = 30 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Hold Time tH 1.5 ns VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Hold Time tH 2 ns VCC = 2.5 V ±0.2 V, CL = 30 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Pulse Width CP tW 3.3 ns VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Pulse Width CP tW 4 ns VCC = 2.5 V ±0.2 V, CL = 30 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Pulse Width CD and SD tW 3.3 ns VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Pulse Width CD and SD tW 3.6 ns VCC = 2.7 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Pulse Width CD and SD tW 4 ns VCC = 2.5 V ±0.2 V, CL = 30 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Recovery Time tREC 2.5 ns VCC = 3.3 V ±0.3 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Recovery Time tREC 3 ns VCC = 2.7 V, CL = 50 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Recovery Time tREC 4.5 ns VCC = 2.5 V ±0.2 V, CL = 30 pF, RL = 500 Ω, TA = -40 to +85 °C 5
Output to Output Skew tOSHL, tOSLH 1 ns 5
Supply Voltage (Operating / Data Retention) VCC -0.5 7 V 4
DC Input Voltage VI -0.5 7 V 4
DC Output Voltage, Output in HIGH or LOW State VO -0.5 V Upper bound printed as VCC + 0.5 V 4
DC Input Diode Current IIK -50 mA VI < GND 4
DC Output Diode Current IOK -50 mA VO < GND 4
DC Output Diode Current IOK 50 mA VO > VCC 4
DC Output Source/Sink Current IO -50 50 mA 4
DC Supply Current per Supply Pin ICC -100 100 mA 4
Storage Temperature TSTG -65 150 °C 4
Supply Voltage, Operating VCC 2 3.6 V Operating 4
Supply Voltage, Data Retention VCC 1.5 3.6 V Data retention 4
Input Voltage VI 0 5.5 V 4
Output Voltage, HIGH or LOW State VO 0 V Upper bound printed as VCC 4
Output Current IOH / IOL IOH / IOL -24 24 mA VCC = 3.0 V-3.6 V 4
Output Current IOH / IOL IOH / IOL -12 12 mA VCC = 2.7 V-3.0 V 4
Output Current IOH / IOL IOH / IOL -8 8 mA VCC = 2.3 V-2.7 V 4
Free-Air Operating Temperature TA -40 85 °C 4
Input Edge Rate Δt/ΔV 0 10 ns/V VIN = 0.8 V-2.0 V, VCC = 3.0 V 4

CAD (KiCad official)

  • Symbol: 74LCX74MTC
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lcx74mtc-etched.step / 74lcx74mtc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lcx74mtc.step / 74lcx74mtc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (13 pp, sha256 97135364336c5527, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF