component

74LCX373FT

Public Made by Adom

by adom

TOSHIBA Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74lcx373ftfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers 74lcx373ft: viewers · Ray 5d ago
74lcx373ft-etched.glb Publish 0.1.0 · Ray 5d ago
74lcx373ft-etched.step 74lcx373ft: factory component page (tier=lcsc) · Ray 5d ago
74lcx373ft-hero.glb 74lcx373ft: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
74lcx373ft-hero.overlay.json Publish 0.1.0 · Ray 5d ago
74lcx373ft.glb Publish 0.1.0 · Ray 5d ago
74lcx373ft.kicad_mod Publish 0.1.0 · Ray 5d ago
74lcx373ft.kicad_sym Publish 0.1.0 · Ray 5d ago
74lcx373ft.lbr Publish 0.1.0 · Ray 5d ago
74lcx373ft.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

74LCX373FT

TOSHIBA · Latches · TSSOP-20

74LCX373FT from TOSHIBA, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable input; when high, the eight outputs are in a high-impedance state.
2 Q0 tri_state 3-state latch output 0, high-impedance when OE is high; 5-V tolerant.
3 D0 input Data input 0 of the octal D-type latch; 5-V tolerant.
4 D1 input Data input 1 of the octal D-type latch; 5-V tolerant.
5 Q1 tri_state 3-state latch output 1, high-impedance when OE is high; 5-V tolerant.
6 Q2 tri_state 3-state latch output 2, high-impedance when OE is high; 5-V tolerant.
7 D2 input Data input 2 of the octal D-type latch; 5-V tolerant.
8 D3 input Data input 3 of the octal D-type latch; 5-V tolerant.
9 Q3 tri_state 3-state latch output 3, high-impedance when OE is high; 5-V tolerant.
10 GND power_in Ground pin (0 V).
11 LE input Latch enable input; Q outputs are latched when LE is taken to a low logic level.
12 Q4 tri_state 3-state latch output 4, high-impedance when OE is high; 5-V tolerant.
13 D4 input Data input 4 of the octal D-type latch; 5-V tolerant.
14 D5 input Data input 5 of the octal D-type latch; 5-V tolerant.
15 Q5 tri_state 3-state latch output 5, high-impedance when OE is high; 5-V tolerant.
16 Q6 tri_state 3-state latch output 6, high-impedance when OE is high; 5-V tolerant.
17 D6 input Data input 6 of the octal D-type latch; 5-V tolerant.
18 D7 input Data input 7 of the octal D-type latch; 5-V tolerant.
19 Q7 tri_state 3-state latch output 7, high-impedance when OE is high; 5-V tolerant.
20 VCC power_in Supply voltage pin; operating range 1.65 to 3.6 V.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 6.5 V 4
Input voltage VIN -0.5 6.5 V 4
Output voltage VOUT -0.5 6.5 V Note 1: Output in OFF state 4
Output voltage VOUT -0.5 V Note 2: High or low state; upper limit printed as VCC + 0.5 4
Input diode current IIK -50 mA 4
Output diode current IOK -50 50 mA Note 3: VOUT < GND, VOUT > VCC 4
Output current IOUT -50 50 mA 4
Power dissipation PD 180 mW 4
VCC/ground current ICC/IGND -100 100 mA 4
Storage temperature Tstg -65 150 4
Supply voltage VCC 1.65 3.6 V Note 1: Data retention only 4
Input voltage VIN 1.5 3.6 V 4
Output voltage VOUT 0 5.5 V Note 2: Output in OFF state 4
Output voltage VOUT 0 V Note 3: High or low state; upper limit printed as VCC 4
Output current IOUT -24 24 mA Note 4: VCC = 3.0 to 3.6 V 4
Output current IOUT -12 12 mA Note 5: VCC = 2.7 to 3.0 V 4
Operating temperature Topr -40 85 4
Input rise and fall times dt/dv 0 10 ns/V Note 6: VIN = 0.8 to 2.0 V, VCC = 3.0 V 4
High-level input voltage VIH 1.7 V VCC = 2.3 to 2.7 V 5
High-level input voltage VIH 2 V VCC = 2.7 to 3.6 V 5
Low-level input voltage VIL 0.7 V VCC = 2.3 to 2.7 V 5
Low-level input voltage VIL 0.8 V VCC = 2.7 to 3.6 V 5
High-level output voltage VOH 1.05 V VIN = VIH or VIL; IOH = -4 mA; VCC = 1.65 V 5
High-level output voltage VOH 1.7 V VIN = VIH or VIL; IOH = -8 mA; VCC = 2.3 V 5
High-level output voltage VOH 2.2 V VIN = VIH or VIL; IOH = -12 mA; VCC = 2.7 V 5
High-level output voltage VOH 2.4 V VIN = VIH or VIL; IOH = -18 mA; VCC = 3.0 V 5
Low-level output voltage VOL 0.2 V VIN = VIH or VIL; IOL = 100 µA; VCC = 1.65 to 3.6 V 5
Low-level output voltage VOL 0.45 V VIN = VIH or VIL; IOL = 4 mA; VCC = 1.65 V 5
Low-level output voltage VOL 0.7 V VIN = VIH or VIL; IOL = 8 mA; VCC = 2.3 V 5
Low-level output voltage VOL 0.4 V VIN = VIH or VIL; IOL = 12 mA; VCC = 2.7 V 5
Low-level output voltage VOL 0.55 V VIN = VIH or VIL; IOL = 24 mA; VCC = 3.0 V 5
Input leakage current IIN -5 5 µA VIN = 0 to 5.5 V; VCC = 1.65 to 3.6 V 5
3-state output OFF-state leakage current IOZ -5 5 µA VIN = VIH or VIL; VOUT = 0 to 5.5 V; VCC = 1.65 to 3.6 V 5
Power-OFF leakage current IOFF 10 µA VIN/VOUT = 5.5 V; VCC = 0 5
Quiescent supply current ICC 10 µA VIN = VCC or GND; VCC = 1.65 to 3.6 V 5
Unidentified leakage-type limit (symbol not attributable) -10 10 µA VCC = 1.65 to 3.6 V 5
Quiescent supply current (per input) ΔICC 500 µA VIN/VOUT = 3.6 to 5.5 V; VIH = VCC - 0.6 V (per input); VCC = 2.7 to 3.6 V 5
Propagation delay time (D-Q) tPLH,tPHL 30 ns VCC = 1.8 ± 0.15 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Propagation delay time (D-Q) tPLH,tPHL 10 ns VCC = 2.5 ± 0.2 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Propagation delay time (D-Q) tPLH,tPHL 9 ns VCC = 2.7 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Propagation delay time (D-Q) tPLH,tPHL 1.5 8 ns VCC = 3.3 ± 0.3 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Propagation delay time (LE-Q) tPLH,tPHL 30 ns VCC = 1.8 ± 0.15 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Propagation delay time (LE-Q) tPLH,tPHL 10.5 ns VCC = 2.5 ± 0.2 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Propagation delay time (LE-Q) tPLH,tPHL 9.5 ns VCC = 2.7 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Propagation delay time (LE-Q) tPLH,tPHL 1.5 8.5 ns VCC = 3.3 ± 0.3 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Output enable time tPZL,tPZH 34 ns VCC = 1.8 ± 0.15 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.2, Table 12.6.1 6
Output enable time tPZL,tPZH 17 ns VCC = 2.5 ± 0.2 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.2, Table 12.6.1 6
Output enable time tPZL,tPZH 9.5 ns VCC = 2.7 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.2, Table 12.6.1 6
Output enable time tPZL,tPZH 1.5 8.5 ns VCC = 3.3 ± 0.3 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.2, Table 12.6.1 6
Minimum pulse width (LE) tw(H) 12 ns VCC = 1.8 ± 0.15 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Minimum pulse width (LE) tw(H) 6 ns VCC = 2.5 ± 0.2 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Minimum pulse width (LE) tw(H) 4 ns VCC = 2.7 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Minimum pulse width (LE) tw(H) 3.3 ns VCC = 3.3 ± 0.3 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Minimum setup time tS 10 ns VCC = 1.8 ± 0.15 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Minimum setup time tS 5 ns VCC = 2.5 ± 0.2 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Minimum setup time tS 2.5 ns VCC = 2.7 V; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6
Output skew tosLH,tosHL 1 ns VCC = 3.3 ± 0.3 V; Parameter guaranteed by design; See 12.5 AC Test Circuit, Table 12.5.1, Fig. 12.6.1, Table 12.6.1 6

CAD (KiCad official)

  • Symbol: 74LCX373FT
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lcx373ft-etched.step / 74lcx373ft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lcx373ft.step / 74lcx373ft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (10 pp, sha256 c330aebfa852fdbc, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF