component
74LCX125YTTR
Public Made by Adomby adom
STMicroelectronics Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.
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74LCX125YTTR
STMicroelectronics · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
74LCX125YTTR from STMicroelectronics, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1G | input | Output enable input for gate 1; setting G high places output 1Y in the high impedance state. |
| 2 | 1A | input | Data input for gate 1, 5 V tolerant per the device features. |
| 3 | 1Y | tri_state | Data output for gate 1, 3-state, with symmetrical output drive of |
| 4 | 2G | input | Output enable input for gate 2; setting G high places output 2Y in the high impedance state. |
| 5 | 2A | input | Data input for gate 2, 5 V tolerant per the device features. |
| 6 | 2Y | tri_state | Data output for gate 2, 3-state, with symmetrical output drive of |
| 7 | GND | power_in | Ground (0 V) reference pin. |
| 8 | 3Y | tri_state | Data output for gate 3, 3-state, with symmetrical output drive of |
| 9 | 3A | input | Data input for gate 3, 5 V tolerant per the device features. |
| 10 | 3G | input | Output enable input for gate 3; setting G high places output 3Y in the high impedance state. |
| 11 | 4Y | tri_state | Data output for gate 4, 3-state, with symmetrical output drive of |
| 12 | 4A | input | Data input for gate 4, 5 V tolerant per the device features. |
| 13 | 4G | input | Output enable input for gate 4; setting G high places output 4Y in the high impedance state. |
| 14 | VCC | power_in | Positive supply voltage, with recommended operating range of 2.0 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| DC input voltage | VI | -0.5 | 7 | V | 5 | ||
| DC output voltage (VCC = 0 V) | VO | -0.5 | 7 | V | VCC = 0 V | 5 | |
| DC output voltage (high or low state), max printed as VCC + 0.5 V | VO | -0.5 | V | high or low state | 5 | ||
| DC input diode current | IIK | -50 | mA | 5 | |||
| DC output diode current | IOK | -50 | mA | VO < GND | 5 | ||
| DC output current | IO | -50 | 50 | mA | 5 | ||
| DC supply current per supply pin | ICC | -100 | 100 | mA | 5 | ||
| DC ground current per supply pin | IGND | -100 | 100 | mA | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Lead temperature | TL | 300 | °C | 10 s | 5 | ||
| Supply voltage | VCC | 2 | 3.6 | V | 5 | ||
| Input voltage | VI | 0 | 5.5 | V | 5 | ||
| Output voltage (VCC = 0 V) | VO | 0 | 5.5 | V | VCC = 0 V | 5 | |
| Output voltage (high or low state), max printed as VCC | VO | 0 | V | high or low state | 5 | ||
| High or low level output current | IOH, IOL | -24 | 24 | mA | VCC = 3.0 to 3.6 V | 5 | |
| High or low level output current | IOH, IOL | -12 | 12 | mA | VCC = 2.7 V | 5 | |
| Input rise and fall time | dt/dv | 0 | 10 | ns/V | VIN from 0.8 V to 2 V at VCC = 3.0 V | 5 | |
| High level input voltage | VIH | 2 | V | VCC 2.7 to 3.6 V; -40 to 85 °C | 6 | ||
| Low level input voltage | VIL | 0.8 | V | VCC 2.7 to 3.6 V; -40 to 85 °C | 6 | ||
| High level output voltage | VOH | 2.2 | V | VCC 2.7 V; IO = -12 mA; -40 to 85 °C | 6 | ||
| High level output voltage | VOH | 2.4 | V | VCC 3.0 V; IO = -18 mA; -40 to 85 °C | 6 | ||
| Low level output voltage | VOL | 0.2 | V | VCC 2.7 to 3.6 V; IO = 100 µA; -40 to 85 °C | 6 | ||
| Low level output voltage | VOL | 0.4 | V | VCC 2.7 V; IO = 12 mA; -40 to 85 °C | 6 | ||
| Low level output voltage | VOL | 0.55 | V | VCC 3.0 V; IO = 24 mA; -40 to 85 °C | 6 | ||
| Input leakage current | II | -5 | 5 | µA | VCC 2.7 to 3.6 V; VI = 0 to 5.5 V; -40 to 85 °C | 6 | |
| Power OFF leakage current | Ioff | 10 | µA | VI or VO = 5.5 V; -40 to 85 °C | 6 | ||
| High impedance output leakage current | IOZ | -5 | 5 | µA | VCC 2.7 to 3.6 V; VI = VIH or VIL; VO = 0 to VCC; -40 to 85 °C | 6 | |
| Quiescent supply current | ICC | 10 | µA | VCC 2.7 to 3.6 V; VI = VCC or GND; -40 to 85 °C | 6 | ||
| Quiescent supply current | ICC | -10 | 10 | µA | VCC 2.7 to 3.6 V; VI or VO = 3.6 to 5.5 V; -40 to 85 °C | 6 | |
| Additional quiescent supply current per input | ΔICC | 500 | µA | VCC 2.7 to 3.6 V; VIH = VCC - 0.6 V; -40 to 85 °C | 6 | ||
| Dynamic low level quiet output | VOLP | 0.8 | V | VCC 3.3 V; CL = 50 pF; VIL = 0 V, VIH = 3.3 V; TA = 25 °C | 6 | ||
| Dynamic low level quiet output | VOLV | -0.8 | V | VCC 3.3 V; CL = 50 pF; VIL = 0 V, VIH = 3.3 V; TA = 25 °C | 6 | ||
| Propagation delay time | tPLH, tPHL | 6 | ns | VCC 2.7 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 | ||
| Propagation delay time | tPLH, tPHL | 5.2 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 1.0 ns; -40 to 85 °C | 7 | ||
| Output enable time to HIGH and LOW level | tPZL, tPZH | 6 | ns | VCC 2.7 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 | ||
| Output enable time to HIGH and LOW level | tPZL, tPZH | 5 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 1.0 ns; -40 to 85 °C | 7 | ||
| Output disable time to HIGH and LOW level | tPLZ, tPHZ | 6 | ns | VCC 2.7 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 | ||
| Output disable time to HIGH and LOW level | tPLZ, tPHZ | 5 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 1.0 ns; -40 to 85 °C | 7 | ||
| Output to output skew time | tOSLH, tOSHL | 1 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 |
CAD (KiCad official)
- Symbol:
74LCX125YTTR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74lcx125yttr-etched.step/74lcx125yttr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lcx125yttr.step/74lcx125yttr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (16 pp, sha256
9a54e677025d61c0, retrieved 2026-11-05, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74LCX125YTTR
**STMicroelectronics** · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
74LCX125YTTR from STMicroelectronics, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1G | input | Output enable input for gate 1; setting G high places output 1Y in the high impedance state. |
| 2 | 1A | input | Data input for gate 1, 5 V tolerant per the device features. |
| 3 | 1Y | tri_state | Data output for gate 1, 3-state, with symmetrical output drive of |IOH| = IOL = 24 mA (min.) at VCC = 3 V. |
| 4 | 2G | input | Output enable input for gate 2; setting G high places output 2Y in the high impedance state. |
| 5 | 2A | input | Data input for gate 2, 5 V tolerant per the device features. |
| 6 | 2Y | tri_state | Data output for gate 2, 3-state, with symmetrical output drive of |IOH| = IOL = 24 mA (min.) at VCC = 3 V. |
| 7 | GND | power_in | Ground (0 V) reference pin. |
| 8 | 3Y | tri_state | Data output for gate 3, 3-state, with symmetrical output drive of |IOH| = IOL = 24 mA (min.) at VCC = 3 V. |
| 9 | 3A | input | Data input for gate 3, 5 V tolerant per the device features. |
| 10 | 3G | input | Output enable input for gate 3; setting G high places output 3Y in the high impedance state. |
| 11 | 4Y | tri_state | Data output for gate 4, 3-state, with symmetrical output drive of |IOH| = IOL = 24 mA (min.) at VCC = 3 V. |
| 12 | 4A | input | Data input for gate 4, 5 V tolerant per the device features. |
| 13 | 4G | input | Output enable input for gate 4; setting G high places output 4Y in the high impedance state. |
| 14 | VCC | power_in | Positive supply voltage, with recommended operating range of 2.0 V to 3.6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 5 |
| DC input voltage | VI | -0.5 | | 7 | V | | 5 |
| DC output voltage (VCC = 0 V) | VO | -0.5 | | 7 | V | VCC = 0 V | 5 |
| DC output voltage (high or low state), max printed as VCC + 0.5 V | VO | -0.5 | | | V | high or low state | 5 |
| DC input diode current | IIK | -50 | | | mA | | 5 |
| DC output diode current | IOK | -50 | | | mA | VO < GND | 5 |
| DC output current | IO | -50 | | 50 | mA | | 5 |
| DC supply current per supply pin | ICC | -100 | | 100 | mA | | 5 |
| DC ground current per supply pin | IGND | -100 | | 100 | mA | | 5 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 5 |
| Lead temperature | TL | | | 300 | °C | 10 s | 5 |
| Supply voltage | VCC | 2 | | 3.6 | V | | 5 |
| Input voltage | VI | 0 | | 5.5 | V | | 5 |
| Output voltage (VCC = 0 V) | VO | 0 | | 5.5 | V | VCC = 0 V | 5 |
| Output voltage (high or low state), max printed as VCC | VO | 0 | | | V | high or low state | 5 |
| High or low level output current | IOH, IOL | -24 | | 24 | mA | VCC = 3.0 to 3.6 V | 5 |
| High or low level output current | IOH, IOL | -12 | | 12 | mA | VCC = 2.7 V | 5 |
| Input rise and fall time | dt/dv | 0 | | 10 | ns/V | VIN from 0.8 V to 2 V at VCC = 3.0 V | 5 |
| High level input voltage | VIH | 2 | | | V | VCC 2.7 to 3.6 V; -40 to 85 °C | 6 |
| Low level input voltage | VIL | | | 0.8 | V | VCC 2.7 to 3.6 V; -40 to 85 °C | 6 |
| High level output voltage | VOH | 2.2 | | | V | VCC 2.7 V; IO = -12 mA; -40 to 85 °C | 6 |
| High level output voltage | VOH | 2.4 | | | V | VCC 3.0 V; IO = -18 mA; -40 to 85 °C | 6 |
| Low level output voltage | VOL | | | 0.2 | V | VCC 2.7 to 3.6 V; IO = 100 µA; -40 to 85 °C | 6 |
| Low level output voltage | VOL | | | 0.4 | V | VCC 2.7 V; IO = 12 mA; -40 to 85 °C | 6 |
| Low level output voltage | VOL | | | 0.55 | V | VCC 3.0 V; IO = 24 mA; -40 to 85 °C | 6 |
| Input leakage current | II | -5 | | 5 | µA | VCC 2.7 to 3.6 V; VI = 0 to 5.5 V; -40 to 85 °C | 6 |
| Power OFF leakage current | Ioff | | | 10 | µA | VI or VO = 5.5 V; -40 to 85 °C | 6 |
| High impedance output leakage current | IOZ | -5 | | 5 | µA | VCC 2.7 to 3.6 V; VI = VIH or VIL; VO = 0 to VCC; -40 to 85 °C | 6 |
| Quiescent supply current | ICC | | | 10 | µA | VCC 2.7 to 3.6 V; VI = VCC or GND; -40 to 85 °C | 6 |
| Quiescent supply current | ICC | -10 | | 10 | µA | VCC 2.7 to 3.6 V; VI or VO = 3.6 to 5.5 V; -40 to 85 °C | 6 |
| Additional quiescent supply current per input | ΔICC | | | 500 | µA | VCC 2.7 to 3.6 V; VIH = VCC - 0.6 V; -40 to 85 °C | 6 |
| Dynamic low level quiet output | VOLP | | | 0.8 | V | VCC 3.3 V; CL = 50 pF; VIL = 0 V, VIH = 3.3 V; TA = 25 °C | 6 |
| Dynamic low level quiet output | VOLV | -0.8 | | | V | VCC 3.3 V; CL = 50 pF; VIL = 0 V, VIH = 3.3 V; TA = 25 °C | 6 |
| Propagation delay time | tPLH, tPHL | | | 6 | ns | VCC 2.7 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 |
| Propagation delay time | tPLH, tPHL | | | 5.2 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 1.0 ns; -40 to 85 °C | 7 |
| Output enable time to HIGH and LOW level | tPZL, tPZH | | | 6 | ns | VCC 2.7 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 |
| Output enable time to HIGH and LOW level | tPZL, tPZH | | | 5 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 1.0 ns; -40 to 85 °C | 7 |
| Output disable time to HIGH and LOW level | tPLZ, tPHZ | | | 6 | ns | VCC 2.7 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 |
| Output disable time to HIGH and LOW level | tPLZ, tPHZ | | | 5 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 1.0 ns; -40 to 85 °C | 7 |
| Output to output skew time | tOSLH, tOSHL | | | 1 | ns | VCC 3.0 to 3.6 V; CL 50 pF; RL 500 Ω; ts = tr 2.5 ns; -40 to 85 °C | 7 |
## CAD (KiCad official)
- Symbol: `74LCX125YTTR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74lcx125yttr-etched.step` / `74lcx125yttr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lcx125yttr.step` / `74lcx125yttr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/74lcx125yttr.pdf) (16 pp, sha256 `9a54e677025d61c0`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74lcx125yttr-datasheet.pdf)