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74HCT74D

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by adom

Nexperia Flip Flops, SO-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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74HCT74D

Nexperia · Flip Flops · SO-14

74HCT74D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1RD input Asynchronous reset-direct input for flip-flop 1, active LOW.
2 1D input Data input for flip-flop 1, sampled on the LOW-to-HIGH clock transition.
3 1CP input Clock input for flip-flop 1, LOW-to-HIGH edge-triggered with Schmitt-trigger action.
4 1SD input Asynchronous set-direct input for flip-flop 1, active LOW.
5 1Q output True output of flip-flop 1.
6 1Q output Complement output of flip-flop 1.
7 GND power_in Ground (0 V) reference for all voltages.
8 2Q output Complement output of flip-flop 2.
9 2Q output True output of flip-flop 2.
10 2SD input Asynchronous set-direct input for flip-flop 2, active LOW.
11 2CP input Clock input for flip-flop 2, LOW-to-HIGH edge-triggered with Schmitt-trigger action.
12 2D input Data input for flip-flop 2, sampled on the LOW-to-HIGH clock transition.
13 2RD input Asynchronous reset-direct input for flip-flop 2, active LOW.
14 VCC power_in Supply voltage; 2.0 V to 6.0 V for 74HC74 and 4.5 V to 5.5 V for 74HCT74 in the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SO-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 5
Ambient temperature Tamb -40 25 125 °C 5
Input voltage VI 0 V 5
Output voltage VO 0 V 5
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
Supply voltage absolute maximum VCC -0.5 7 V 5
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 5
Supply current absolute maximum ICC 100 mA 5
Ground current IGND -100 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C; SOT108-1 (SO14) package 5
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +85 °C 6
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C 6
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +85 °C 6
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C 6
HIGH-level output voltage VOH 3.84 4.32 V VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; Tamb = -40 °C to +85 °C 6
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; Tamb = -40 °C to +125 °C 6
LOW-level output voltage VOL 0.15 0.33 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; Tamb = -40 °C to +85 °C 6
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; Tamb = -40 °C to +125 °C 6
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; Tamb = -40 °C to +85 °C 6
Supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +85 °C 6
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +125 °C 6
Additional supply current per nD, nRD input pin ΔICC 70 315 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; nD, nRD inputs; Tamb = -40 °C to +85 °C 6
Additional supply current per nD, nRD input pin ΔICC 343 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; nD, nRD inputs; Tamb = -40 °C to +125 °C 6
Additional supply current per nSD, nCP input pin ΔICC 80 360 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; nSD, nCP input; Tamb = -40 °C to +85 °C 6
Additional supply current per nSD, nCP input pin ΔICC 392 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; nSD, nCP input; Tamb = -40 °C to +125 °C 6
Propagation delay nCP to nQ, nQ tpd 18 44 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +85 °C 9
Propagation delay nCP to nQ, nQ tpd 53 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 9
Propagation delay nSD to nQ, nQ tpd 23 50 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +85 °C 9
Propagation delay nSD to nQ, nQ tpd 60 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +125 °C 9
Propagation delay nRD to nQ, nQ tpd 24 50 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +85 °C 9
Propagation delay nRD to nQ, nQ tpd 60 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +125 °C 9
Transition time nQ, nQ tt 7 19 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +85 °C 9
Transition time nQ, nQ tt 22 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 9
Pulse width nCP HIGH or LOW tW 23 9 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +85 °C 9
Pulse width nCP HIGH or LOW tW 27 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 9
Pulse width nSD, nRD LOW tW 20 9 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +85 °C 9
Pulse width nSD, nRD LOW tW 24 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +125 °C 9
Recovery time nSD, nRD trec 8 1 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +85 °C 9
Recovery time nSD, nRD trec 9 ns VCC = 4.5 V; see Fig. 6; Tamb = -40 °C to +125 °C 9
Set-up time nD to nCP tsu 15 5 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +85 °C 9
Set-up time nD to nCP tsu 18 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 9
Hold time nD to nCP th 3 -3 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +85 °C 9
Hold time nD to nCP th 3 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 9
Maximum clock frequency nCP fmax 22 54 MHz VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +85 °C 9
Maximum clock frequency nCP fmax 18 MHz VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 9
Power dissipation capacitance CPD 29 pF CL = 50 pF; f = 1 MHz; VI = GND to VCC - 1.5 V 9
Propagation delay nCP to nQ, nQ tpd 15 ns VCC = 5 V; CL = 15 pF 9
Propagation delay nSD to nQ, nQ tpd 18 ns VCC = 5 V; CL = 15 pF 9
Propagation delay nRD to nQ, nQ tpd 18 ns VCC = 5 V; CL = 15 pF 9
Maximum clock frequency nCP fmax 59 MHz VCC = 5 V; CL = 15 pF 9
Input capacitance CI 3.5 pF 6

CAD (KiCad official)

  • Symbol: 74HCT74D
  • Footprint: Package_SO:SO-14_3.9x8.65mm_P1.27mm
  • 3D model: SO-14 (KiCad packages3D, STEP)
  • 3D model files: 74hct74d-etched.step / 74hct74d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct74d.step / 74hct74d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 1e4ab9833ba6e6a3, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF