74HCT595D

{
  "slug": "74hct595d",
  "version": "0.2.1",
  "type": "component",
  "description": "Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "74hct595d"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "74hct595d.kicad_sym",
    "74hct595d.kicad_mod",
    "74hct595d.glb",
    "74hct595d.step",
    "74hct595d-etched.step",
    "74hct595d.lbr",
    "docs/hero.png",
    "docs/74hct595d-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pads.json",
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  "component": {
    "mpn": "74HCT595D",
    "manufacturer": "Nexperia",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HCT595D.pdf",
    "parts": {
      "symbol": "74hct595d.kicad_sym",
      "footprint": "74hct595d.kicad_mod",
      "model_3d": "74hct595d-hero.glb",
      "model_3d_plain": "74hct595d.glb",
      "model_3d_step": "74hct595d-etched.step",
      "model_3d_step_plain": "74hct595d.step",
      "lbr": "74hct595d.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "Q1",
        "type": "tri_state",
        "description": "Parallel data output 1. 3-state output from the storage register; high-impedance when OE is HIGH. Bus driver output rated approximately 6 mA at VCC = 4.5 V."
      },
      {
        "number": "2",
        "name": "Q2",
        "type": "tri_state",
        "description": "Parallel data output 2. 3-state output from the storage register; high-impedance when OE is HIGH."
      },
      {
        "number": "3",
        "name": "Q3",
        "type": "tri_state",
        "description": "Parallel data output 3. 3-state output from the storage register; high-impedance when OE is HIGH."
      },
      {
        "number": "4",
        "name": "Q4",
        "type": "tri_state",
        "description": "Parallel data output 4. 3-state output from the storage register; high-impedance when OE is HIGH."
      },
      {
        "number": "5",
        "name": "Q5",
        "type": "tri_state",
        "description": "Parallel data output 5. 3-state output from the storage register; high-impedance when OE is HIGH."
      },
      {
        "number": "6",
        "name": "Q6",
        "type": "tri_state",
        "description": "Parallel data output 6. 3-state output from the storage register; high-impedance when OE is HIGH."
      },
      {
        "number": "7",
        "name": "Q7",
        "type": "tri_state",
        "description": "Parallel data output 7 (MSB of the storage register). 3-state output; high-impedance when OE is HIGH."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Max ground current 70 mA."
      },
      {
        "number": "9",
        "name": "Q7S",
        "type": "output",
        "description": "Serial data output. Provides the Q6S contents of the shift register (one clock ahead of Q7) to enable cascading multiple 595s. Rated approximately 4 mA at VCC = 4.5 V; not 3-state (always active)."
      },
      {
        "number": "10",
        "name": "MR",
        "type": "input",
        "description": "Master reset, active LOW. Asynchronously clears the shift register only; does not affect the storage register or parallel outputs directly. TTL-compatible input."
      },
      {
        "number": "11",
        "name": "SHCP",
        "type": "input",
        "description": "Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP. Typical fmax ~91 MHz at VCC = 4.5 V."
      },
      {
        "number": "12",
        "name": "STCP",
        "type": "input",
        "description": "Storage register clock input (latch clock). On the LOW-to-HIGH transition, the contents of the shift register are transferred to the 8-bit storage register (parallel output latch)."
      },
      {
        "number": "13",
        "name": "OE",
        "type": "input",
        "description": "Output enable, active LOW. When LOW, storage register contents appear on Q0-Q7; when HIGH, the parallel outputs enter high-impedance OFF-state. Does not affect the shift or storage register state."
      },
      {
        "number": "14",
        "name": "DS",
        "type": "input",
        "description": "Serial data input. Sampled by the shift register on the rising edge of SHCP. TTL-compatible input."
      },
      {
        "number": "15",
        "name": "Q0",
        "type": "tri_state",
        "description": "Parallel data output 0 (LSB of the storage register). 3-state output; high-impedance when OE is HIGH."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage. Operating range 4.5 V to 5.5 V for 74HCT595 (JESD8C compliant). Absolute maximum -0.5 V to +7 V. Typical ICC ~80 uA at VCC = 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://assets.nexperia.com/documents/data-sheet/74HCT595D.pdf",
        "pages": 21,
        "sha256": "fa24207e780cd8c4",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HCT595",
      "logic_family": "74HCT",
      "function_code": "595",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit SIPO Shift Register with Output Latch",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "74hct595d.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74hct595d-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "e36f669ccb1c4c5ce4ffe625e20618a86551c373f10868921e31aa18e9938eda",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "title": "74HCT595D",
  "brief": "Nexperia Shifting Register, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "metadata": {
    "specs": {
      "Manufacturer": "Nexperia",
      "Package": "SOIC-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "discovery_triggers": [
    "74hct595d"
  ],
  "discovery_pitch": "74HCT595D (Nexperia) component page with datasheet-verified CAD.",
  "visibility": "public"
}