component

74HCT595D-Q100

Public Made by Adom

by adom

Nexperia Registers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic ics74hct595d-q100factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
74hct595d-q100 / README.md
History Download
Ray Publish 0.1.0 b275068 8d ago

74HCT595D-Q100

Nexperia · Registers · SO-16

74HCT595D-Q100 from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output 1 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
2 Q2 tri_state Parallel data output 2 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
3 Q3 tri_state Parallel data output 3 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
4 Q4 tri_state Parallel data output 4 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
5 Q5 tri_state Parallel data output 5 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
6 Q6 tri_state Parallel data output 6 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
7 Q7 tri_state Parallel data output 7 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
8 GND power_in Ground (0 V).
9 Q7S output Serial data output for cascading, output current limit ±25 mA.
10 MR input Master reset, active LOW; a LOW resets the shift register.
11 SHCP input Shift register clock input; data shifts on LOW-to-HIGH transitions.
12 STCP input Storage register clock input; shift register data transfers to storage register on LOW-to-HIGH transition.
13 OE input Output enable input, active LOW; a HIGH puts the Qn outputs in high-impedance OFF-state.
14 DS input Serial data input.
15 Q0 tri_state Parallel data output 0 with 3-state bus driver, high-impedance when OE is HIGH, output current limit ±35 mA.
16 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended for 74HCT595-Q100 (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SO-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 5
Input clamping current IIK 20 mA VI < -0.5 V or VI > VCC + 0.5 V; ±20 5
Output clamping current IOK 20 mA VO < -0.5 V or VO > VCC + 0.5 V; ±20 5
Output current pin Q7S IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V); pin Q7S 5
Output current pins Qn IO -35 35 mA VO = -0.5 V to (VCC + 0.5 V); pins Qn 5
Supply current ICC 70 mA 5
Ground current IGND -70 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW SOT109-1; derates linearly with 12.4 mW/K above 110 °C 5
Supply voltage VCC 4.5 5 5.5 V 74HCT595-Q100 6
Input voltage VI 0 V max = VCC 6
Output voltage VO 0 V max = VCC 6
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 6
Ambient temperature Tamb -40 25 125 °C 6
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 7
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 7
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +85 °C 7
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +125 °C 7
HIGH-level output voltage Q7S VOH 3.84 4.32 V VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; -40 °C to +85 °C 7
HIGH-level output voltage Q7S VOH 3.7 V VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; -40 °C to +125 °C 7
HIGH-level output voltage Qn VOH 3.7 4.32 V VI = VIH or VIL; VCC = 4.5 V; IO = -6 mA; -40 °C to +85 °C 7
HIGH-level output voltage Qn VOH 3.7 V VI = VIH or VIL; VCC = 4.5 V; IO = -6 mA; -40 °C to +125 °C 7
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +85 °C 7
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +125 °C 7
LOW-level output voltage Q7S VOL 0.15 0.33 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; -40 °C to +85 °C 7
LOW-level output voltage Q7S VOL 0.4 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; -40 °C to +125 °C 7
LOW-level output voltage Qn VOL 0.16 0.33 V VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; -40 °C to +85 °C 7
LOW-level output voltage Qn VOL 0.4 V VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; -40 °C to +125 °C 7
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C 8
OFF-state output current IOZ -5 5 μA VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +85 °C 8
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +125 °C 8
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C 8
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 8
Additional supply current MR, SHCP, STCP, OE ΔICC 150 675 μA VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +85 °C 8
Additional supply current MR, SHCP, STCP, OE ΔICC 735 μA VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +125 °C 8
Additional supply current DS ΔICC 25 113 μA VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +85 °C 8
Additional supply current DS ΔICC 123 μA VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; IO = 0 A; -40 °C to +125 °C 8
Propagation delay SHCP to Q7S tpd 25 42 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Propagation delay SHCP to Q7S tpd 53 ns VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 10
Propagation delay SHCP to Q7S tpd 63 ns VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 10
Propagation delay STCP to Qn tpd 24 40 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Propagation delay STCP to Qn tpd 50 ns VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 10
Propagation delay STCP to Qn tpd 60 ns VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 10
Propagation delay MR to Q7S tPHL 23 40 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Propagation delay MR to Q7S tPHL 50 ns VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 10
Propagation delay MR to Q7S tPHL 60 ns VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 10
Enable time OE to Qn ten 21 35 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Enable time OE to Qn ten 44 ns VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 10
Enable time OE to Qn ten 53 ns VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 10
Disable time OE to Qn tdis 18 30 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Disable time OE to Qn tdis 38 ns VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 10
Disable time OE to Qn tdis 45 ns VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 10
Pulse width SHCP HIGH or LOW tW 16 6 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Pulse width STCP HIGH or LOW tW 16 5 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Pulse width MR LOW tW 20 8 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Set-up time DS to SHCP tsu 16 5 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Set-up time SHCP to STCP tsu 16 8 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Hold time DS to SHCP th 3 -2 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Recovery time MR to SHCP trec 10 -7 ns VCC = 4.5 V to 5.5 V; 25 °C 10
Maximum frequency SHCP and STCP fmax 30 52 MHz VCC = 4.5 V to 5.5 V; 25 °C 10
Maximum frequency SHCP and STCP fmax 24 MHz VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 10
Maximum frequency SHCP and STCP fmax 20 MHz VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 10
Input capacitance CI 3.5 pF 8
Power dissipation capacitance CPD 130 pF fi = 1 MHz; VI = GND to VCC - 1.5 V; all 9 outputs switching 10

CAD (KiCad official)

  • Symbol: 74HCT595D-Q100
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SO-16 (KiCad packages3D, STEP)
  • 3D model files: 74hct595d-q100-etched.step / 74hct595d-q100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct595d-q100.step / 74hct595d-q100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 ccdb88dc8760d451, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF