component
74HCT574PW
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HCT574PW
Nexperia · Flip Flops · TSSOP-20
74HCT574PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | 3-state output enable input, active LOW; a HIGH forces Q0 to Q7 into the high-impedance OFF-state without changing the flip-flop contents. |
| 2 | D0 | input | Data input 0, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 3 | D1 | input | Data input 1, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 4 | D2 | input | Data input 2, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 5 | D3 | input | Data input 3, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 6 | D4 | input | Data input 4, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 7 | D5 | input | Data input 5, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 8 | D6 | input | Data input 6, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 9 | D7 | input | Data input 7, sampled on the LOW-to-HIGH CP transition and must meet the set-up and hold time requirements; inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 11 | CP | input | Clock input; the flip-flops store their D inputs on the LOW-to-HIGH clock transition. |
| 12 | Q7 | tri_state | 3-state non-inverting flip-flop output 7; high-impedance when OE is HIGH. |
| 13 | Q6 | tri_state | 3-state non-inverting flip-flop output 6; high-impedance when OE is HIGH. |
| 14 | Q5 | tri_state | 3-state non-inverting flip-flop output 5; high-impedance when OE is HIGH. |
| 15 | Q4 | tri_state | 3-state non-inverting flip-flop output 4; high-impedance when OE is HIGH. |
| 16 | Q3 | tri_state | 3-state non-inverting flip-flop output 3; high-impedance when OE is HIGH. |
| 17 | Q2 | tri_state | 3-state non-inverting flip-flop output 2; high-impedance when OE is HIGH. |
| 18 | Q1 | tri_state | 3-state non-inverting flip-flop output 1; high-impedance when OE is HIGH. |
| 19 | Q0 | tri_state | 3-state non-inverting flip-flop output 0; high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage; recommended range is 4.5 V to 5.5 V for 74HCT574 (2.0 V to 6.0 V for 74HC574). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output current | IO | -35 | 35 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| Supply current | ICC | 70 | mA | 4 | |||
| Ground current | IGND | -70 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Total power dissipation | Ptot | 500 | mW | SOT360-1 (TSSOP20): derates linearly with 10.0 mW/K above 100 °C | 4 | ||
| Supply voltage (74HCT574) | VCC | 4.5 | 5 | 5.5 | V | 74HCT574 column | 4 |
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 74HCT574 column | 4 |
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| HIGH-level input voltage | VIH | 2 | 1.6 | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| LOW-level input voltage | VIL | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C | 6 | |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -6 mA; 25 °C | 6 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C | 6 | |
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; 25 °C | 6 | |
| Input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 5.5 V; 25 °C | 6 | |
| OFF-state output current | IOZ | -0.5 | 0.5 | μA | VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; 25 °C | 6 | |
| Supply current | ICC | 8 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 6 | ||
| Additional supply current per Dn input | ΔICC | 50 | 180 | μA | VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; Dn inputs; 25 °C | 6 | |
| Additional supply current per OE input | ΔICC | 125 | 450 | μA | VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; OE input; 25 °C | 6 | |
| Additional supply current per CP input | ΔICC | 150 | 540 | μA | VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; CP input; 25 °C | 6 | |
| Propagation delay CP to Qn | tpd | 18 | 33 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 5; 25 °C | 8 | |
| Enable time OE to Qn | ten | 19 | 33 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7; 25 °C | 8 | |
| Disable time OE to Qn | tdis | 16 | 28 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7; 25 °C | 8 | |
| Transition time Qn | tt | 5 | 12 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 5; 25 °C | 8 | |
| Pulse width CP HIGH or LOW | tW | 16 | 7 | ns | VCC = 4.5 V; see Fig. 6; 25 °C | 8 | |
| Set-up time Dn to CP | tsu | 12 | 3 | ns | VCC = 4.5 V; see Fig. 6; 25 °C | 8 | |
| Hold time Dn to CP | th | 5 | -1 | ns | VCC = 4.5 V; see Fig. 6; 25 °C | 8 | |
| Maximum frequency CP | fmax | 30 | 69 | MHz | VCC = 4.5 V; 25 °C | 8 | |
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -6 mA; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; -40 °C to +125 °C | 6 | ||
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 5.5 V; -40 °C to +125 °C | 6 | |
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +125 °C | 6 | |
| Supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 6 | ||
| Additional supply current per Dn input | ΔICC | 245 | μA | VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; Dn inputs; -40 °C to +125 °C | 6 | ||
| Additional supply current per OE input | ΔICC | 613 | μA | VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; OE input; -40 °C to +125 °C | 6 | ||
| Additional supply current per CP input | ΔICC | 735 | μA | VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; CP input; -40 °C to +125 °C | 6 | ||
| Propagation delay CP to Qn | tpd | 50 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C | 8 | ||
| Enable time OE to Qn | ten | 50 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7; -40 °C to +125 °C | 8 | ||
| Disable time OE to Qn | tdis | 42 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7; -40 °C to +125 °C | 8 | ||
| Transition time Qn | tt | 18 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C | 8 | ||
| Pulse width CP HIGH or LOW | tW | 24 | ns | VCC = 4.5 V; see Fig. 6; -40 °C to +125 °C | 8 | ||
| Set-up time Dn to CP | tsu | 18 | ns | VCC = 4.5 V; see Fig. 6; -40 °C to +125 °C | 8 | ||
| Hold time Dn to CP | th | 5 | ns | VCC = 4.5 V; see Fig. 6; -40 °C to +125 °C | 8 | ||
| Maximum frequency CP | fmax | 20 | MHz | VCC = 4.5 V; -40 °C to +125 °C | 8 |
CAD (KiCad official)
- Symbol:
74HCT574PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74hct574pw-etched.step/74hct574pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct574pw.step/74hct574pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (17 pp, sha256
2cb7f0c355e59666, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).