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74HCT574D

Public Made by Adom

by adom

Nexperia Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HCT574D

Nexperia · Flip Flops · SOIC-20-300mil

74HCT574D from Nexperia, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input 3-state output enable input (active LOW); a HIGH on OE forces Q0 to Q7 into the high-impedance OFF-state without changing the flip-flop contents.
2 D0 input Data input 0 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
3 D1 input Data input 1 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
4 D2 input Data input 2 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
5 D3 input Data input 3 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
6 D4 input Data input 4 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
7 D5 input Data input 5 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
8 D6 input Data input 6 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
9 D7 input Data input 7 to the flip-flop, which is stored on the LOW-to-HIGH clock transition when set-up and hold times are met.
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 CP input Clock input; the flip-flops capture the D inputs on the LOW-to-HIGH (positive edge) transition.
12 Q7 tri_state 3-state flip-flop output 7, high-impedance when OE is HIGH.
13 Q6 tri_state 3-state flip-flop output 6, high-impedance when OE is HIGH.
14 Q5 tri_state 3-state flip-flop output 5, high-impedance when OE is HIGH.
15 Q4 tri_state 3-state flip-flop output 4, high-impedance when OE is HIGH.
16 Q3 tri_state 3-state flip-flop output 3, high-impedance when OE is HIGH.
17 Q2 tri_state 3-state flip-flop output 2, high-impedance when OE is HIGH.
18 Q1 tri_state 3-state flip-flop output 1, high-impedance when OE is HIGH.
19 Q0 tri_state 3-state flip-flop output 0, high-impedance when OE is HIGH.
20 VCC power_in Supply voltage; the 74HCT574 is recommended for 4.5 V to 5.5 V operation (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-20-300mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIH HIGH-level input voltage (25 °C) VIH 2 1.6 V VCC = 4.5 V to 5.5 V; 25 °C 6
VIH HIGH-level input voltage (-40 °C to +125 °C) VIH 2 V VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 6
VIL LOW-level input voltage (25 °C) VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; 25 °C 6
VIL LOW-level input voltage (-40 °C to +125 °C) VIL 0.8 V VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 6
HIGH-level output voltage (25 °C) VOH 4.4 4.5 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C 6
HIGH-level output voltage (-40 °C to +125 °C) VOH 4.4 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +125 °C 6
HIGH-level output voltage (25 °C) VOH 3.98 4.32 V VI = VIH or VIL; VCC = 4.5 V; IO = -6 mA; 25 °C 6
HIGH-level output voltage (-40 °C to +125 °C) VOH 3.7 V VI = VIH or VIL; VCC = 4.5 V; IO = -6 mA; -40 °C to +125 °C 6
LOW-level output voltage (25 °C) VOL 0 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C 6
LOW-level output voltage (-40 °C to +125 °C) VOL 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +125 °C 6
LOW-level output voltage (25 °C) VOL 0.16 0.26 V VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; 25 °C 6
LOW-level output voltage (-40 °C to +125 °C) VOL 0.4 V VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; -40 °C to +125 °C 6
input leakage current (25 °C) II -0.1 0.1 μA VI = VCC or GND; VCC = 5.5 V; 25 °C 6
input leakage current (-40 °C to +125 °C) II -1 1 μA VI = VCC or GND; VCC = 5.5 V; -40 °C to +125 °C 6
OFF-state output current (25 °C) IOZ -0.5 0.5 μA VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; 25 °C 6
OFF-state output current (-40 °C to +125 °C) IOZ -10 10 μA VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +125 °C 6
supply current (25 °C) ICC 8 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C 6
supply current (-40 °C to +125 °C) ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 6
additional supply current per input pin, Dn inputs (25 °C) ΔICC 50 180 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; Dn inputs; 25 °C 6
additional supply current per input pin, Dn inputs (-40 °C to +125 °C) ΔICC 245 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; Dn inputs; -40 °C to +125 °C 6
additional supply current per input pin, OE input (25 °C) ΔICC 125 450 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; OE input; 25 °C 6
additional supply current per input pin, OE input (-40 °C to +125 °C) ΔICC 613 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; OE input; -40 °C to +125 °C 6
additional supply current per input pin, CP input (25 °C) ΔICC 150 540 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; CP input; 25 °C 6
additional supply current per input pin, CP input (-40 °C to +125 °C) ΔICC 735 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin; CP input; -40 °C to +125 °C 6
propagation delay CP to Qn (25 °C) tpd 18 33 ns CP to Qn; see Fig. 5; VCC = 4.5 V; 25 °C 8
propagation delay CP to Qn (-40 °C to +125 °C) tpd 50 ns CP to Qn; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C 8
enable time OE to Qn (25 °C) ten 19 33 ns OE to Qn; see Fig. 7; VCC = 4.5 V; 25 °C 8
enable time OE to Qn (-40 °C to +125 °C) ten 50 ns OE to Qn; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 8
disable time OE to Qn (25 °C) tdis 16 28 ns OE to Qn; see Fig. 7; VCC = 4.5 V; 25 °C 8
disable time OE to Qn (-40 °C to +125 °C) tdis 42 ns OE to Qn; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 8
transition time (25 °C) tt 5 12 ns Qn; see Fig. 5; VCC = 4.5 V; 25 °C 8
transition time (-40 °C to +125 °C) tt 18 ns Qn; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C 8
pulse width (25 °C) tW 16 7 ns CP HIGH or LOW; see Fig. 6; VCC = 4.5 V; 25 °C 8
pulse width (-40 °C to +125 °C) tW 24 ns CP HIGH or LOW; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C 8
set-up time (25 °C) tsu 12 3 ns Dn to CP; see Fig. 6; VCC = 4.5 V; 25 °C 8
set-up time (-40 °C to +125 °C) tsu 18 ns Dn to CP; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C 8
hold time (25 °C) th 5 -1 ns Dn to CP; see Fig. 6; VCC = 4.5 V; 25 °C 8
hold time (-40 °C to +125 °C) th 5 ns Dn to CP; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C 8
maximum frequency (25 °C) fmax 30 69 MHz CP; see Fig. 5; VCC = 4.5 V; 25 °C 8
maximum frequency (-40 °C to +125 °C) fmax 20 MHz CP; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C 8
supply voltage VCC 4.5 5 5.5 V 4
input voltage VI 0 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 25 125 °C 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -35 35 mA VO = -0.5 V to (VCC + 0.5 V) 4
supply current ICC 70 mA 4
ground current IGND -70 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW 4

CAD (KiCad official)

  • Symbol: 74HCT574D
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: 74hct574d-etched.step / 74hct574d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct574d.step / 74hct574d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 2cb7f0c355e59666, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF