component

74HCT573PW

Public Made by Adom

by adom

Nexperia Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74HCT573PW

Nexperia · Latches · TSSOP-20

74HCT573PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input 3-state output enable input, active LOW. When LOW the Q0..Q7 outputs are enabled; when HIGH all outputs are placed in high-impedance OFF-state. Does not affect latch contents.
2 D0 input Data input bit 0 to latch 1. TTL-level input; latched on the HIGH-to-LOW transition of LE and passed transparently to Q0 while LE is HIGH.
3 D1 input Data input bit 1 to latch 2. TTL-level input; latched on the HIGH-to-LOW transition of LE.
4 D2 input Data input bit 2 to latch 3. TTL-level input; latched on the HIGH-to-LOW transition of LE.
5 D3 input Data input bit 3 to latch 4. TTL-level input; latched on the HIGH-to-LOW transition of LE.
6 D4 input Data input bit 4 to latch 5. TTL-level input; latched on the HIGH-to-LOW transition of LE.
7 D5 input Data input bit 5 to latch 6. TTL-level input; latched on the HIGH-to-LOW transition of LE.
8 D6 input Data input bit 6 to latch 7. TTL-level input; latched on the HIGH-to-LOW transition of LE.
9 D7 input Data input bit 7 to latch 8. TTL-level input; latched on the HIGH-to-LOW transition of LE.
10 GND power_in Ground reference, 0 V. All voltages in the device are referenced to this pin.
11 LE input Latch Enable input, active HIGH. When HIGH the latches are transparent (Qn follows Dn); on the HIGH-to-LOW transition the data present at Dn (meeting set-up/hold) is stored.
12 Q7 tri_state 3-state latch output bit 7. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
13 Q6 tri_state 3-state latch output bit 6. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
14 Q5 tri_state 3-state latch output bit 5. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
15 Q4 tri_state 3-state latch output bit 4. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
16 Q3 tri_state 3-state latch output bit 3. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
17 Q2 tri_state 3-state latch output bit 2. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
18 Q1 tri_state 3-state latch output bit 1. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
19 Q0 tri_state 3-state latch output bit 0. Non-inverting; driven when OE is LOW, high-impedance when OE is HIGH.
20 VCC power_in Supply voltage. Recommended operating range for 74HCT573 is 4.5 V to 5.5 V (absolute max 7 V). Bypass locally with a 100 nF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • 74HCT573PW
  • 74HCT573PWD
  • 74HCT573PWBQ

CAD (KiCad official)

  • Symbol: 74HCT573PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hct573pw-etched.step / 74hct573pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct573pw.step / 74hct573pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 2feaa6991e6dc5d6, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF