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Contents

README

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74HCT4851BQ-Q100

Nexperia · Analog Switches, Multiplexers · DHVQFN-16-EP(2.5x3.5)

74HCT4851BQ-Q100 from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y4 bidirectional Independent analog input/output channel 4 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit VCC + 0.5 V and -0.5 V).
2 Y6 bidirectional Independent analog input/output channel 6 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
3 Z bidirectional Common analog input/output that connects to the selected Yn channel when E is LOW; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
4 Y7 bidirectional Independent analog input/output channel 7 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
5 Y5 bidirectional Independent analog input/output channel 5 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
6 E input Active-LOW enable input; when HIGH all switches are OFF regardless of S0 to S2, and the HIGH-level input must meet VIH (for 74HCT4851-Q100, minimum 2.0 V at VCC = 4.5 V to 5.5 V).
7 n.c. unconnected Not connected; the datasheet specifies no electrical function for this terminal.
8 GND power_in Ground reference (0 V) for all voltages in the datasheet.
9 S2 input Select input, most significant bit of the channel address (with E LOW, S2 S1 S0 choose Y0 to Y7 per the function table); input voltage must stay within 0 V to VCC.
10 S1 input Select input, middle bit of the channel address (with E LOW, S2 S1 S0 choose Y0 to Y7 per the function table); input voltage must stay within 0 V to VCC.
11 S0 input Select input, least significant bit of the channel address (with E LOW, S2 S1 S0 choose Y0 to Y7 per the function table); input voltage must stay within 0 V to VCC.
12 Y3 bidirectional Independent analog input/output channel 3 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
13 Y0 bidirectional Independent analog input/output channel 0 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
14 Y1 bidirectional Independent analog input/output channel 1 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
15 Y2 bidirectional Independent analog input/output channel 2 of the 8-channel switch; switch voltage must stay within 0 V to VCC (absolute limit -0.5 V to VCC + 0.5 V).
16 VCC power_in Supply voltage: recommended 2.0 V to 6.0 V for 74HC4851-Q100 and 4.5 V to 5.5 V for 74HCT4851-Q100; absolute maximum -0.5 V to +7.0 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Interface
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
ICC supply current (absolute maximum) ICC 50 mA 5
IGND ground current (absolute maximum) IGND -50 mA 5
IIK input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
ISK switch clamping current ISK -20 20 mA VSW < -0.5 V or VSW > VCC + 0.5 V 5
ISW switch current ISW -25 25 mA VSW > -0.5 V or VSW < VCC + 0.5 V 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
Supply voltage (absolute maximum) VCC -0.5 7 V 5
Input voltage (absolute maximum) VI -0.5 V 5
Switch voltage (absolute maximum) VSW -0.5 V 5
Supply voltage VCC 4.5 5 5.5 V 74HCT4851-Q100 6
Input voltage VI 0 V 74HCT4851-Q100 6
Switch voltage VSW 0 V 74HCT4851-Q100 6
Ambient temperature Tamb -40 125 °C 6
Input transition rise and fall rate Δt/ΔV 500 ns/V VCC = 4.5 V 6
ON resistance (peak) RON(peak) 76 210 Ω VI = VCC to GND; E = VIL; VCC = 4.5 V; ISW ≤ 2 mA; Tamb 25 °C 6
ON resistance (peak) RON(peak) 76 270 Ω VI = VCC to GND; E = VIL; VCC = 4.5 V; ISW ≤ 2 mA; Tamb -40 °C to +125 °C 6
ON resistance mismatch between channels ΔRON 2 8 Ω VI = 0.5 × VCC; E = VIL; VCC = 4.5 V; ISW ≤ 2 mA; Tamb 25 °C 6
ON resistance mismatch between channels ΔRON 2 16 Ω VI = 0.5 × VCC; E = VIL; VCC = 4.5 V; ISW ≤ 2 mA; Tamb -40 °C to +125 °C 6
Output voltage variation (injection current) ΔVO -1 0.03 1 mV Tamb = -40 °C to +125 °C; /ISW/ ≤ 1 mA; RS ≤ 3.9 kΩ; VCC = 5.0 V 7
Output voltage variation (injection current) ΔVO -5 0.27 5 mV Tamb = -40 °C to +125 °C; /ISW/ ≤ 10 mA; RS ≤ 3.9 kΩ; VCC = 5.0 V 7
Output voltage variation (injection current) ΔVO -2 0.03 2 mV Tamb = -40 °C to +125 °C; /ISW/ ≤ 1 mA; RS ≤ 20 kΩ; VCC = 5.0 V 7
Output voltage variation (injection current) ΔVO -20 0.48 20 mV Tamb = -40 °C to +125 °C; /ISW/ ≤ 10 mA; RS ≤ 20 kΩ; VCC = 5.0 V 7
HIGH-level input voltage VIH 2 V control inputs; VCC = 4.5 V to 5.5 V; Tamb 25 °C 8
LOW-level input voltage VIL 0.8 V control inputs; VCC = 4.5 V to 5.5 V; Tamb 25 °C 8
Input leakage current (control inputs) II -0.1 0.1 μA control inputs; VI = GND or VCC; VCC = 5.5 V; Tamb 25 °C 8
Input leakage current (control inputs) II -1 1 μA control inputs; VI = GND or VCC; VCC = 5.5 V; Tamb -40 °C to +125 °C 8
Input leakage current (per channel) II -0.1 0.1 μA per channel; E = VIH; VI = GND or VCC; VO = VCC or GND; VCC = 5.5 V; see Fig. 4; Tamb 25 °C 8
Input leakage current (per channel) II -1 1 μA per channel; E = VIH; VI = GND or VCC; VO = VCC or GND; VCC = 5.5 V; see Fig. 4; Tamb -40 °C to +125 °C 8
OFF-state leakage current IS(OFF) -0.2 0.2 μA all channels; Tamb 25 °C 8
OFF-state leakage current IS(OFF) -4 4 μA all channels; Tamb -40 °C to +125 °C 8
ON-state leakage current IS(ON) -0.1 0.1 μA E = VIL; VI = GND or VCC; VO = VCC or GND; VCC = 5.5 V; see Fig. 5; Tamb 25 °C 8
ON-state leakage current IS(ON) -1 1 μA E = VIL; VI = GND or VCC; VO = VCC or GND; VCC = 5.5 V; see Fig. 5; Tamb -40 °C to +125 °C 8
Supply current ICC 2 μA VI = GND or VCC; VCC = 5.5 V; Tamb 25 °C 8
Supply current ICC 20 μA VI = GND or VCC; VCC = 5.5 V; Tamb -40 °C to +125 °C 8
Additional supply current ΔICC 300 μA control inputs; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; Tamb 25 °C 8
Additional supply current ΔICC 370 μA control inputs; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; Tamb -40 °C to +125 °C 8
Input capacitance CI 2 10 pF S0, S1, S2 and E; Tamb 25 °C 8
Input capacitance CI 10 pF S0, S1, S2 and E; Tamb -40 °C to +125 °C 8
Switch capacitance Csw 15 40 pF switch Z; OFF-state; Tamb 25 °C 8
Switch capacitance Csw 40 pF switch Z; OFF-state; Tamb -40 °C to +125 °C 8
Switch capacitance Cyn 3 15 pF Yn; OFF-state; Tamb 25 °C 8
Switch capacitance Cyn 15 pF Yn; OFF-state; Tamb -40 °C to +125 °C 8
Propagation delay (Z to Yn, Yn to Z) tpd 1.6 3.7 11.5 ns Z to Yn, Yn to Z; VCC = 4.5 V; see Fig. 8; Tamb 25 °C 11
Propagation delay (Z to Yn, Yn to Z) tpd 1.1 13.5 ns Z to Yn, Yn to Z; VCC = 4.5 V; see Fig. 8; Tamb -40 °C to +125 °C 11
Propagation delay (Sn to Z, Sn to Yn) tpd 3.2 8 13 ns Sn to Z, Sn to Yn; VCC = 4.5 V; see Fig. 9; Tamb 25 °C 11
Propagation delay (Sn to Z, Sn to Yn) tpd 2.3 17 ns Sn to Z, Sn to Yn; VCC = 4.5 V; see Fig. 9; Tamb -40 °C to +125 °C 11
Enable time ten 4.2 8.6 25 ns E to Z, E to Yn; VCC = 4.5 V; see Fig. 10; Tamb 25 °C 11
Enable time ten 3 35 ns E to Z, E to Yn; VCC = 4.5 V; see Fig. 10; Tamb -40 °C to +125 °C 11
Disable time tdis 28.5 64.7 80 ns E to Z, E to Yn; VCC = 4.5 V; see Fig. 10; Tamb 25 °C 11
Disable time tdis 28 100 ns E to Z, E to Yn; VCC = 4.5 V; see Fig. 10; Tamb -40 °C to +125 °C 11

CAD (KiCad official)

  • Symbol: 74HCT4851BQ-Q100
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74hct4851bq-q100-etched.step / 74hct4851bq-q100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct4851bq-q100.step / 74hct4851bq-q100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 0b621ccffb78d38f, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF