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74HCT4514PW

Public Made by Adom

by adom

Nexperia Signal Switches, Multiplexers, Decoders, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HCT4514PW

Nexperia · Signal Switches, Multiplexers, Decoders · TSSOP-24

74HCT4514PW from Nexperia, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LE input Latch enable input (active HIGH): when LOW, the last data on A0 to A3 is stored in the latches and the outputs remain stable.
2 A0 input Binary-weighted address input A0 for selecting one of the 16 outputs; it is latched when LE goes LOW.
3 A1 input Binary-weighted address input A1 for selecting one of the 16 outputs; it is latched when LE goes LOW.
4 Q7 output Multiplexer output Q7 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
5 Q6 output Multiplexer output Q6 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
6 Q5 output Multiplexer output Q5 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
7 Q4 output Multiplexer output Q4 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
8 Q3 output Multiplexer output Q3 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
9 Q1 output Multiplexer output Q1 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
10 Q2 output Multiplexer output Q2 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
11 Q0 output Multiplexer output Q0 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
12 GND power_in Ground (0 V) reference for all voltages.
13 Q13 output Multiplexer output Q13 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
14 Q12 output Multiplexer output Q12 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
15 Q15 output Multiplexer output Q15 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
16 Q14 output Multiplexer output Q14 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
17 Q9 output Multiplexer output Q9 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
18 Q8 output Multiplexer output Q8 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
19 Q11 output Multiplexer output Q11 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
20 Q10 output Multiplexer output Q10 (active HIGH); it is HIGH only when E is LOW and the latched address selects it.
21 A2 input Binary-weighted address input A2 for selecting one of the 16 outputs; it is latched when LE goes LOW.
22 A3 input Binary-weighted address input A3 for selecting one of the 16 outputs; it is latched when LE goes LOW.
23 E input Enable input (active LOW): when LOW the latched output selected by the address is HIGH, and when HIGH all outputs are LOW without affecting the latch.
24 VCC power_in Supply voltage: recommended 2.0 V to 6.0 V for 74HC4514 and 4.5 V to 5.5 V for 74HCT4514, with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-24
Category Logic
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC 4.5 5 5.5 V 6
input voltage VI 0 V 6
output voltage VO 0 V 6
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 6
ambient temperature Tamb -40 125 °C 6
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; +25 °C 7
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; −40 °C to +125 °C 7
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; +25 °C 7
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; −40 °C to +125 °C 7
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = −20 μA; VCC = 4.5 V; +25 °C 7
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = −20 μA; VCC = 4.5 V; −40 °C to +125 °C 7
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; IO = −4 mA; VCC = 4.5 V; +25 °C 7
HIGH-level output voltage VOH 3.84 V VI = VIH or VIL; IO = −4 mA; VCC = 4.5 V; −40 °C to +85 °C 7
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = −4 mA; VCC = 4.5 V; −40 °C to +125 °C 7
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; −40 °C to +125 °C 7
LOW-level output voltage VOL 0.15 0.26 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; +25 °C 7
LOW-level output voltage VOL 0.33 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; −40 °C to +85 °C 7
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; −40 °C to +125 °C 7
input leakage current II -0.1 0.1 μA VI = VCC or GND; VCC = 5.5 V; +25 °C 7
input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; −40 °C to +125 °C 7
supply current ICC 8 μA VI = VCC or GND; VCC = 5.5 V; IO = 0 A; +25 °C 7
supply current ICC 80 μA VI = VCC or GND; VCC = 5.5 V; IO = 0 A; −40 °C to +85 °C 7
supply current ICC 160 μA VI = VCC or GND; VCC = 5.5 V; IO = 0 A; −40 °C to +125 °C 7
additional supply current, An input ΔICC 65 234 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; +25 °C 7
additional supply current, An input ΔICC 292.5 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; −40 °C to +85 °C 7
additional supply current, An input ΔICC 318.5 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; −40 °C to +125 °C 7
additional supply current, LE input ΔICC 140 504 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; +25 °C 7
additional supply current, LE input ΔICC 630 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; −40 °C to +85 °C 7
additional supply current, LE input ΔICC 686 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; −40 °C to +125 °C 7
additional supply current, E input ΔICC 100 360 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; +25 °C 7
additional supply current, E input ΔICC 450 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; −40 °C to +85 °C 7
additional supply current, E input ΔICC 490 μA per input pin; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 A; −40 °C to +125 °C 7
propagation delay An to Qn tpd 30 55 ns An to Qn; VCC = 4.5 V; +25 °C; see Fig. 5 9
propagation delay An to Qn tpd 69 ns An to Qn; VCC = 4.5 V; −40 °C to +85 °C; see Fig. 5 9
propagation delay An to Qn tpd 83 ns An to Qn; VCC = 4.5 V; −40 °C to +125 °C; see Fig. 5 9
propagation delay LE to Qn tpd 29 50 ns LE to Qn; VCC = 4.5 V; +25 °C; see Fig. 5 9
propagation delay LE to Qn tpd 63 ns LE to Qn; VCC = 4.5 V; −40 °C to +85 °C; see Fig. 5 9
propagation delay LE to Qn tpd 75 ns LE to Qn; VCC = 4.5 V; −40 °C to +125 °C; see Fig. 5 9
propagation delay E to Qn tpd 17 40 ns E to Qn; VCC = 4.5 V; +25 °C; see Fig. 5 9
propagation delay E to Qn tpd 50 ns E to Qn; VCC = 4.5 V; −40 °C to +85 °C; see Fig. 5 9
propagation delay E to Qn tpd 60 ns E to Qn; VCC = 4.5 V; −40 °C to +125 °C; see Fig. 5 9
transition time Qn tt 7 15 ns Qn; VCC = 4.5 V; +25 °C; see Fig. 5 9
transition time Qn tt 19 ns Qn; VCC = 4.5 V; −40 °C to +85 °C; see Fig. 5 9
transition time Qn tt 22 ns Qn; VCC = 4.5 V; −40 °C to +125 °C; see Fig. 5 9
pulse width LE HIGH tW 16 4 ns LE HIGH; VCC = 4.5 V; +25 °C; see Fig. 6 9
pulse width LE HIGH tW 20 ns LE HIGH; VCC = 4.5 V; −40 °C to +85 °C; see Fig. 6 9
pulse width LE HIGH tW 24 ns LE HIGH; VCC = 4.5 V; −40 °C to +125 °C; see Fig. 6 9
set-up time An to LE tsu 18 9 ns An to LE; VCC = 4.5 V; +25 °C; see Fig. 6 9
set-up time An to LE tsu 23 ns An to LE; VCC = 4.5 V; −40 °C to +85 °C; see Fig. 6 9
set-up time An to LE tsu 27 ns An to LE; VCC = 4.5 V; −40 °C to +125 °C; see Fig. 6 9
hold time An to LE th 3 -3 ns An to LE; VCC = 4.5 V; +25 °C; see Fig. 6 9
hold time An to LE th 3 ns An to LE; VCC = 4.5 V; −40 °C to +125 °C; see Fig. 6 9
supply voltage VCC -0.5 7 V 5
input clamping current IIK -20 20 mA VI < −0.5 V or VI > VCC + 0.5 V 5
output clamping current IOK -20 20 mA VO < −0.5 V or VO > VCC + 0.5 V 5
output current IO -25 25 mA −0.5 V < VO < VCC + 0.5 V 5
supply current ICC 50 mA 5
ground current IGND -50 mA 5
storage temperature Tstg -65 150 °C 5
total power dissipation Ptot 500 mW SOT355-1 (TSSOP24): derates 12.4 mW/K above 110 °C 5

CAD (KiCad official)

  • Symbol: 74HCT4514PW
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: 74hct4514pw-etched.step / 74hct4514pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct4514pw.step / 74hct4514pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 fbe3c25cee37fe68, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF