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74HCT393D

Public Made by Adom

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Nexperia Counters, Dividers, SO-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74HCT393D

Nexperia · Counters, Dividers · SO-14

74HCT393D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP input Clock input for counter 1, which is edge-triggered and advances the counter on the HIGH-to-LOW transition.
2 1MR input Asynchronous master reset input for counter 1, active HIGH, which clears the counter stages and forces the outputs LOW independent of 1CP.
3 1Q0 output Flip-flop output Q0 of counter 1, the least significant bit of the 4-bit binary count (count sequence in Table 3).
4 1Q1 output Flip-flop output Q1 of counter 1, bit 1 of the 4-bit binary count (count sequence in Table 3).
5 1Q2 output Flip-flop output Q2 of counter 1, bit 2 of the 4-bit binary count (count sequence in Table 3).
6 1Q3 output Flip-flop output Q3 of counter 1, the most significant bit of the 4-bit binary count (count sequence in Table 3).
7 GND power_in Ground reference at 0 V; all voltages are referenced to GND.
8 2Q3 output Flip-flop output Q3 of counter 2, the most significant bit of the 4-bit binary count (count sequence in Table 3).
9 2Q2 output Flip-flop output Q2 of counter 2, bit 2 of the 4-bit binary count (count sequence in Table 3).
10 2Q1 output Flip-flop output Q1 of counter 2, bit 1 of the 4-bit binary count (count sequence in Table 3).
11 2Q0 output Flip-flop output Q0 of counter 2, the least significant bit of the 4-bit binary count (count sequence in Table 3).
12 2MR input Asynchronous master reset input for counter 2, active HIGH, which clears the counter stages and forces the outputs LOW independent of 2CP.
13 2CP input Clock input for counter 2, which is edge-triggered and advances the counter on the HIGH-to-LOW transition.
14 VCC power_in Supply voltage; recommended range is 2.0 V to 6.0 V for 74HC393 and 4.5 V to 5.5 V for 74HCT393, with an absolute maximum of +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SO-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage (recommended) VCC 4.5 5 5.5 V 74HCT393 5
input voltage (recommended) VI 0 V referenced to GND; upper limit printed as VCC 5
output voltage (recommended) VO 0 V referenced to GND; upper limit printed as VCC 5
ambient temperature Tamb -40 25 125 °C 5
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
supply voltage (absolute maximum) VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA VO = -0.5 V to VCC + 0.5 V 4
supply current ICC -50 50 mA 4
ground current IGND -50 50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW [1] SO14 (SOT108-1) derates 10.1 mW/K above 100 °C 4
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; 25 °C 6
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; 25 °C 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C 6
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; 25 °C 6
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; -40 °C to +125 °C 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C 6
LOW-level output voltage VOL 0.15 0.26 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; 25 °C 6
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; -40 °C to +125 °C 6
input leakage current II -0.1 0.1 μA VI = VCC or GND; VCC = 5.5 V; 25 °C 6
input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; -40 °C to +125 °C 6
supply current ICC 8 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C 6
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 6
additional supply current per input pin nCP ΔICC 40 144 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin nCP; 25 °C 6
additional supply current per input pin nCP ΔICC 196 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin nCP; -40 °C to +125 °C 6
additional supply current per input pin nMR ΔICC 100 360 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin nMR; 25 °C 6
additional supply current per input pin nMR ΔICC 490 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A; per input pin nMR; -40 °C to +125 °C 6
propagation delay nCP to nQ0 tpd 15 25 ns nCP to nQ0; see Fig. 9; VCC = 4.5 V; CL = 50 pF; 25 °C 7
propagation delay nCP to nQ0 tpd 38 ns nCP to nQ0; see Fig. 9; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 7
propagation delay nQx to nQ(x+1) tpd 6 10 ns nQx to nQ(x+1); see Fig. 9; VCC = 4.5 V; CL = 50 pF; 25 °C 7
propagation delay nQx to nQ(x+1) tpd 15 ns nQx to nQ(x+1); see Fig. 9; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 7
HIGH to LOW propagation delay nMR to nQx tPHL 18 32 ns nMR to nQx; see Fig. 10; VCC = 4.5 V; CL = 50 pF; 25 °C 7
HIGH to LOW propagation delay nMR to nQx tPHL 48 ns nMR to nQx; see Fig. 10; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 7
transition time Qn tt 7 15 ns Qn; see Fig. 9; VCC = 4.5 V; CL = 50 pF; 25 °C 7
transition time Qn tt 22 ns Qn; see Fig. 9; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 7
pulse width nCP HIGH or LOW tW 19 11 ns nCP HIGH or LOW; see Fig. 9; VCC = 4.5 V; 25 °C 8
pulse width nCP HIGH or LOW tW 29 ns nCP HIGH or LOW; see Fig. 9; VCC = 4.5 V; -40 °C to +125 °C 8
pulse width nMR HIGH tW 16 6 ns nMR HIGH; see Fig. 10; VCC = 4.5 V; 25 °C 8
pulse width nMR HIGH tW 24 ns nMR HIGH; see Fig. 10; VCC = 4.5 V; -40 °C to +125 °C 8
recovery time nMR to nCP trec 5 0 ns nMR to nCP; see Fig. 10; VCC = 4.5 V; 25 °C 8
maximum clock frequency fclk(max) 27 48 MHz see Fig. 9; VCC = 4.5 V; 25 °C 8
maximum clock frequency fclk(max) 18 MHz see Fig. 9; VCC = 4.5 V; -40 °C to +125 °C 8

CAD (KiCad official)

  • Symbol: 74HCT393D
  • Footprint: Package_SO:SO-14_3.9x8.65mm_P1.27mm
  • 3D model: SO-14 (KiCad packages3D, STEP)
  • 3D model files: 74hct393d-etched.step / 74hct393d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct393d.step / 74hct393d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 42d273f87d2e5d89, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF